DLPS052 October 2015 DLPA3000
For switching power supplies, the layout is an important step in the design process, especially when it concerns high-peak currents and high-switching frequencies. If the layout is not carefully done, the regulator could show stability issues and/or EMI problems. Therefore, it is recommended to use wide- and short-traces for high-current paths and for their return power ground paths. The input capacitor, output capacitor, and inductor should be placed as near as possible to the IC. In order to minimize ground noise coupling between different buck converters, it is advised to separate their grounds and connect them together at a central point under the part.
The high currents of the buck converters concentrate around pins VIN, SWITCH and PGND (Figure 30). The voltage at the pins VIN, PGND, and FB are DC voltages while the pin SWITCH has a switching voltage between VIN and PGND. In case the FET between pins 52 and 53 is closed, the red line indicates the current flow while the blue line indicates the current flow when the FET between pins 53 and 54 is closed. These paths carry the highest currents and must be kept as short as possible.
The trace to the VIN pin carries high AC currents. Therefore, the trace should be low-resistive to prevent voltage drop across the trace. Additionally, the decoupling capacitors should be placed as near to the VIN pin as possible.
The SWITCH pin is connected alternatingly to the VIN or GND. This means a square wave voltage is present on the SWITCH pin with an amplitude of VIN and containing high frequencies. This can lead to EMI problems if not properly handled. To reduce EMI problems, a snubber network (RSN7 & CSN7) is placed at the SWITCH pin to prevent and/or suppress unwanted high-frequency ringing at the moment of switching.
The PGND pin sinks high current and should be connected to a star ground point such that it does not interfere with other ground connections.
The FB pin is the sense connection for the regulated output voltage, which is a DC voltage; no current is flowing through this pin. The voltage on the FB pin is compared with the internal reference voltage in order to control the loop. The FB connection should be made at the load such that I•R drop is not affecting the sensed voltage.