DLPS071A October   2015  – February 2023 DLPA3005

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Parameters
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Description
    3. 7.3 Feature Description
      1. 7.3.1 Supply and Monitoring
        1. 7.3.1.1 Supply
        2. 7.3.1.2 Monitoring
          1. 7.3.1.2.1 Block Faults
          2. 7.3.1.2.2 Auto LED Turn Off Functionality
          3. 7.3.1.2.3 Thermal Protection
      2. 7.3.2 Illumination
        1. 7.3.2.1 Programmable Gain Block
        2. 7.3.2.2 LDO Illumination
        3. 7.3.2.3 Illumination Driver A
        4. 7.3.2.4 RGB Strobe Decoder
          1. 7.3.2.4.1 Break Before Make (BBM)
          2. 7.3.2.4.2 Openloop Voltage
          3. 7.3.2.4.3 Transient Current Limit
        5. 7.3.2.5 Illumination Monitoring
          1. 7.3.2.5.1 Power Good
          2. 7.3.2.5.2 Ratio Metric Overvoltage Protection
        6. 7.3.2.6 Illumination Driver plus Power FETs Efficiency
      3. 7.3.3 External Power FET Selection
        1. 7.3.3.1 Threshold Voltage
        2. 7.3.3.2 Gate Charge and Gate Timing
        3. 7.3.3.3 RDS(ON)
      4. 7.3.4 DMD Supplies
        1. 7.3.4.1 LDO DMD
        2. 7.3.4.2 DMD HV Regulator
        3. 7.3.4.3 DMD/DLPC Buck Converters
        4. 7.3.4.4 DMD Monitoring
          1. 7.3.4.4.1 Power Good
          2. 7.3.4.4.2 Overvoltage Fault
      5. 7.3.5 Buck Converters
        1. 7.3.5.1 LDO Bucks
        2. 7.3.5.2 General Purpose Buck Converter
        3. 7.3.5.3 Buck Converter Monitoring
          1. 7.3.5.3.1 Power Good
          2. 7.3.5.3.2 Overvoltage Fault
        4. 7.3.5.4 Buck Converter Efficiency
      6. 7.3.6 Auxiliary LDOs
      7. 7.3.7 Measurement System
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 SPI
      2. 7.5.2 Interrupt
      3. 7.5.3 Fast-Shutdown in Case of Fault
      4. 7.5.4 Protected Registers
    6. 7.6 Register Maps
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Component Selection for General-Purpose Buck Converters
      3. 8.2.3 Application Curve
    3. 8.3 System Example With DLPA3005 Internal Block Diagram
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Up and Power-Down Timing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 SPI Connections
      2. 10.1.2 RLIM Routing
      3. 10.1.3 LED Connection
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Third-Party Products Disclaimer
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1.3 LED Connection

High switching currents run through the wiring connecting the external RGB switches and the LEDs. Therefore special attention needs to be paid here. Two perspectives apply to the LED-to-RGB switches wiring:

  1. The resistance of the wiring, Rseries
  2. The inductance of the wiring, Lseries

The location of the parasitic series impedances is depicted in Figure 10-3.

GUID-64C00E54-E2C2-4341-AEC3-37B19531DF88-low.gif Figure 10-3 Parasitic Inductance (LSeries) and Resistance (Rseries) in Series with LED

Currents up to 16 A can run through the wires connecting the LEDs to the RGB switches. Some noticeable dissipation can be caused. Every 10 mΩ of series resistances implies for 16 A average LED current a parasitic power dissipation of 2.5 W. This might cause PCB heating, but more important overall system efficiency is deteriorated.

Additionally the resistance of the wiring might impact the control dynamics of the LED current. It should be noted that the routing resistance is part of the LED current control loop. The LED current is controlled by VLED. For a small change in VLED (ΔVLED) the resulting LED current variation (ΔILED) is given by the total differential resistance in that path, as:

Equation 12.
  • GUID-39915F42-F379-4DFB-AF69-BC7F3D6B3F7D-low.gif

    where

  • rLED is the differential resistance of the LED.
  • Ron_SW_P,Q,R the on resistance of the strobe decoder switch.

In this expression Lseries is ignored since realistic values are usually sufficiently low to cause any noticeable impact on the dynamics.

All the comprising differential resistances are in the range of 12.5 mΩ to several 100’s mΩ. Without paying special attention a series resistance of 100 mΩ can easily be obtained. It is advised to keep this series resistance sufficiently low, that is, <10 mΩ.

The series inductance plays an important role when considering the switched nature of the LED current. While cycling through R,G and B LEDs, the current through these branches is turned-on and turned-off in short time duration. Specifically turning off is fast. A current of 16 A goes to 0 A in a matter of 50 ns. This implies a voltage spike of about 1 V for every 5 nH of parasitic inductance. It is recommended to minimize the series inductance of the LED wiring by:

  • Short wires
  • Thick wires / Multiple parallel wires
  • Small enclosed area of the forward and return current path

If the inductance cannot be made sufficiently low, a Zener diode needs to be used to clamp the drain voltage of the RGB switch such it does not surpass the absolute maximum rating. The clamping voltage need to be chosen between the maximum expected VLED and the absolute maximum rating. Take care of sufficient margin of the clamping voltage relative to the mentioned minimum and maximum voltage.