DLPS054E December   2015  – June 2018 DLPC230-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     DLP553x-Q1 DLP Chipset System Block Diagram
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions – Board Level Test, Debug, and Initialization
    2.     Pin Functions – Parallel Port Input Data and Control
    3.     Pin Functions – OpenLDI Ports Input Data and Control
    4.     Pin Functions – DMD Reset and Bias Control Interfaces
    5.     Pin Functions – DMD Sub-LVDS Interfaces
    6.     Pin Functions – Peripheral Interfaces
    7.     Pin Functions – GPIO Peripheral Interface
    8.     Pin Functions – Clock and PLL Support
    9.     Pin Functions – Power and Ground
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics for Fixed Voltage I/O
    7. 6.7  DMD High-Speed Sub-LVDS Electrical Characteristics
    8. 6.8  DMD Low-Speed Sub-LVDS Electrical Characteristics
    9. 6.9  OpenLDI LVDS Electrical Characteristics
    10. 6.10 Power Dissipation Characterisics
    11. 6.11 System Oscillators Timing Requirements
    12. 6.12 Power Supply and Reset Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 OpenLDI Interface General Timing Requirements
    15. 6.15 Parallel/OpenLDI Interface Frame Timing Requirements
    16. 6.16 Host/Diagnostic Port SPI Interface Timing Requirements
    17. 6.17 Host/Diagnostic Port I2C Interface Timing Requirements
    18. 6.18 Flash Interface Timing Requirements
    19. 6.19 TPS99000-Q1 SPI Interface Timing Requirements
    20. 6.20 TPS99000-Q1 AD3 Interface Timing Requirements
    21. 6.21 Master I2C Port Interface Timing Requirements
    22. 6.22 Chipset Component Usage Specification
  7. Parameter Measurement Information
    1. 7.1 HOST_IRQ Usage Model
    2. 7.2 Input Source
      1. 7.2.1 Supported Input Sources
      2. 7.2.2 Parallel Interface Supported Data Transfer Formats
        1. 7.2.2.1 OpenLDI Interface Supported Data Transfer Formats
          1. 7.2.2.1.1 OpenLDI Interface Bit Mapping Modes
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Parallel Interface
      2. 8.3.2  OpenLDI Interface
      3. 8.3.3  DMD (Sub-LVDS) Interface
      4. 8.3.4  Serial Flash Interface
      5. 8.3.5  Serial Flash Programming
      6. 8.3.6  Host Command and Diagnostic Processor Interfaces
      7. 8.3.7  GPIO Supported Functionality
      8. 8.3.8  Built-In Self Test (BIST)
      9. 8.3.9  EEPROMs
      10. 8.3.10 Temperature Sensor
      11. 8.3.11 Debug Support
    4. 8.4 Device Functional Modes
      1. 8.4.1 Standby Mode
      2. 8.4.2 Display Mode
      3. 8.4.3 Calibration Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Head-Up Display
        1. 9.2.1.1 Design Requirements
      2. 9.2.2 Headlight
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Headlight Video Input
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Management
    2. 10.2 Hot Plug Usage
    3. 10.3 Power Supply Filtering
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  PCB Layout Guidelines for Internal ASIC PLL Power
      2. 11.1.2  DLPC230-Q1 Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3  DMD Interface Layout Considerations
      4. 11.1.4  General PCB Recommendations
      5. 11.1.5  General Handling Guidelines for Unused CMOS-Type Pins
      6. 11.1.6  Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      7. 11.1.7  Number of Layer Changes
      8. 11.1.8  Stubs
      9. 11.1.9  Terminations
      10. 11.1.10 Routing Vias
    2. 11.2 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Device Nomenclature
        1. 12.1.2.1 Device Markings
        2. 12.1.2.2 Video Timing Parameter Definitions
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 DLPC230-Q1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results:
    • Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C4B
  • DMD Display Controller Supporting:
    • DLP5530-Q1 Automotive Interior Display Chipset
    • DLP5531-Q1 Automotive Exterior Lighting Chipset
  • Video Processing
    • Scales Input Image to Match DMD Resolution
    • Bezel Adjustment up ±50% Vertical Image Position and ±10% Horizontal Reducing the Need for Mechanical Alignment (HUD)
    • Support for Pixel Doubling or Quadrupling to Allow Low Resolution Video Input
    • Gamma Correction
  • Embedded Processor With Error Correction (ECC)
    • On-Chip Diagnostic and Self-Test Capability
    • System Diagnostics Including Temperature Monitoring, Device Interface Monitoring, and Photodiode Monitoring
    • Integrated Management of Smooth Dimming
    • Configurable GPIO
  • No External RAM Required, Internal SRAM for Image Processing
  • 600-MHz Sub-LVDS DMD Interface for Low Power and Emission
  • Spread Spectrum Clocking for Reduced EMI
  • Video Input Interface
    • Single OpenLDI (FPD-Link I) Port up
      to 110 MHz
    • 24-bit RGB Parallel Interface up to 110 MHz
  • Configurable Host Control Interface
    • Serial Peripheral Interface (SPI) 10 MHz
    • I2C (400 kHz)
    • Host IRQ Signal to Provide Real-Time Feedback for Critical System Errors
  • Interface to TPS99000-Q1 System Management and Illumination Controller