DLPS030E December   2013  – March 2019 DLPC2607

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Typical Current and Power Dissipation
    6. 6.6  I/O Characteristics
    7. 6.7  Internal Pullup and Pulldown Characteristics
    8. 6.8  Parallel I/F Frame Timing Requirements
    9. 6.9  Parallel I/F General Timing Requirements
    10. 6.10 Parallel I/F Maximum Parallel Interface Horizontal Line Rate
    11. 6.11 BT.656 I/F General Timing Requirements
    12. 6.12 100- to 120-Hz Operational Limitations
    13. 6.13 Flash Interface Timing Requirements
    14. 6.14 DMD Interface Timing Requirements
    15. 6.15 mDDR Memory Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Parallel Bus Interface
      2. 7.3.2 100- to 120-Hz 3-D Display Operation
    4. 7.4 Programming
      1. 7.4.1 Serial Flash Interface
      2. 7.4.2 Serial Flash Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 System Functional Modes
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Reference Clock
        2. 8.2.2.2 mDDR DRAM Compatibility
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Hot-Plug Usage
        2. 8.2.3.2 Maximum Signal Transition Time
        3. 8.2.3.3 Configuration Control
        4. 8.2.3.4 White Point Correction Light Sensor
      4. 8.2.4 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 System Power Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 System Power I/O State Considerations
    4. 9.4 Power-Up Initialization Sequence
    5. 9.5 Power-Good (PARK) Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  Internal ASIC PLL Power
      2. 10.1.2  General Handling Guidelines for Unused CMOS-Type Pins
      3. 10.1.3  SPI Signal Routing
      4. 10.1.4  mDDR Memory and DMD Interface Considerations
      5. 10.1.5  PCB Design
      6. 10.1.6  General PCB Routing (Applies to All Corresponding PCB Signals)
      7. 10.1.7  Maximum, Pin-to-Pin, PCB Interconnects Etch Lengths
      8. 10.1.8  I/F Specific PCB Routing
      9. 10.1.9  Number of Layer Changes
      10. 10.1.10 Stubs
      11. 10.1.11 Termination Requirements:
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Marking
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZVB|176
Thermal pad, mechanical data (Package|Pins)

6.12 100- to 120-Hz Operational Limitations

The table below assumes that a front-end device ahead of the DLPC2607 device converts all 3-D sources to the 3-D format defined previously and provides any needed left-eye or right-eye selection control directly to the 3-D glasses (that is, the DLPC2607 device does not control the glasses). The DLPC2607 device includes a double buffer frame memory, which causes the displayed image to be delayed one frame relative to its input. This requires left or right eye-frame shutter control to be inverted prior to being sent to the glasses.
SOURCE RESOLUTION
(APPL x ALPF)		 MIN FRAME RATE
(Hz)		 NOM FRAME RATE
(Hz)		 MAX FRAME RATE
(Hz)		 MIN TVB (tp_tvb)
(LINES)		 MAX LINE RATE
(kHz)		 MIN LINE RATE
(kHz)		 MIN CLOCK RATE
(MHz)
nHD 640 × 360 99 100 101 12 48  (1)  (2)
WQVGA 427 × 240 99 100 101 12 32  (1)  (2)
QVGA 320 × 240 99 100 101 12 32  (1)  (2)
nHD 640 × 360 118.8 120 121.2 12 48  (1)  (2)
WQVGA 427 × 240 118.8 120 121.2 12 32  (1)  (2)
QVGA 320 × 240 118.8 120 121.2 12 32  (1)  (2)
(1) Use the following equation to determine the minimum line rate for a given application. The application cannot be supported if the calculated minimum line rate exceeds the maximum line rate defined elsewhere in this table;
Line_Rate_min (kHz) = Frame_Rate_max (Hz) × [ALPF + TVB] /1000
Where: TVB = Total vertical blanking (in lines)
ALPF = Active lines per frame
Frame_Rate_max = Max frame rate including all expected wander
(2) The following equation should be used to determine the minimum pixel clock rate for a given application. The application cannot be supported if the calculated minimum pixel clock rate exceeds the max pixel clock rate defined in Parallel I/F General Timing Requirements.
Pixel_Clock_min (MHz) = Line_Rate_max (kHz) × (APPL + 12) / 1000
Where: APPL = Active pixels per line
Line_Rate_max = Max line rate including all expected wander