DLPS030E December 2013 – March 2019 DLPC2607
Refer to the PDF data sheet for device specific package drawings
TI recommends the following guidelines to achieve desired ASIC performance relative to the internal PLL. The DLPC2607 device contains one internal PLL, which has a dedicated analog supply (VDD_PLL and VSS_PLL). Isolate VDD_PLL power and VSS_PLL ground pins using an RC-filter consisting of two 50-Ω series ferrites and two shunt capacitors (to widen the spectrum of noise absorption). TI recommends one 0.1-µF capacitor and that the other is a 0.01-µF capacitor. Place all four components as close to the ASIC as possible; it is especially important to keep the leads of the high-frequency capacitors as short as possible. Note that the user should connect both capacitors across VDD_PLL and VSS_PLL on the ASIC side of the ferrites.
The PCB layout is critical to PLL performance. The ground and power domains are analog signals, and should be treated as such to achieve minimum noise. Therefore, VDD_PLL must be a single trace from the DLPC2607 device to both capacitors, and then through the series ferrites to the power source. Ensure that the power and ground traces are as short as possible, parallel to each other, and as close as possible to each other.