DLPS030E December   2013  – March 2019 DLPC2607

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Typical Current and Power Dissipation
    6. 6.6  I/O Characteristics
    7. 6.7  Internal Pullup and Pulldown Characteristics
    8. 6.8  Parallel I/F Frame Timing Requirements
    9. 6.9  Parallel I/F General Timing Requirements
    10. 6.10 Parallel I/F Maximum Parallel Interface Horizontal Line Rate
    11. 6.11 BT.656 I/F General Timing Requirements
    12. 6.12 100- to 120-Hz Operational Limitations
    13. 6.13 Flash Interface Timing Requirements
    14. 6.14 DMD Interface Timing Requirements
    15. 6.15 mDDR Memory Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Parallel Bus Interface
      2. 7.3.2 100- to 120-Hz 3-D Display Operation
    4. 7.4 Programming
      1. 7.4.1 Serial Flash Interface
      2. 7.4.2 Serial Flash Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 System Functional Modes
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Reference Clock
        2. 8.2.2.2 mDDR DRAM Compatibility
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Hot-Plug Usage
        2. 8.2.3.2 Maximum Signal Transition Time
        3. 8.2.3.3 Configuration Control
        4. 8.2.3.4 White Point Correction Light Sensor
      4. 8.2.4 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 System Power Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 System Power I/O State Considerations
    4. 9.4 Power-Up Initialization Sequence
    5. 9.5 Power-Good (PARK) Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  Internal ASIC PLL Power
      2. 10.1.2  General Handling Guidelines for Unused CMOS-Type Pins
      3. 10.1.3  SPI Signal Routing
      4. 10.1.4  mDDR Memory and DMD Interface Considerations
      5. 10.1.5  PCB Design
      6. 10.1.6  General PCB Routing (Applies to All Corresponding PCB Signals)
      7. 10.1.7  Maximum, Pin-to-Pin, PCB Interconnects Etch Lengths
      8. 10.1.8  I/F Specific PCB Routing
      9. 10.1.9  Number of Layer Changes
      10. 10.1.10 Stubs
      11. 10.1.11 Termination Requirements:
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Marking
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZVB|176
Thermal pad, mechanical data (Package|Pins)

8.2.2.1 Reference Clock

The device requires an external reference clock to feed its internal PLL. This reference may be supplied by a crystal or oscillator. For flexibility, the DLPC2607 device accepts either of two reference clock frequencies (see Table 5), but both must have a maximum frequency variation of 200 ppm (including aging, temperature, and trim component variation). When a crystal is used, the configuration requires several discrete components, as shown in Figure 11.

DLPC2607 reference_clock_dlps30.epsFigure 11. Recommended Crystal Oscillator Configuration

Table 5. Crystal Port Characteristics

PARAMETER NOM UNIT
PLL_REFCLK_I TO GND capacitance 4.5 pF
PLL_REFCLK_O TO GND capacitance 4.5 pF

Table 6. Recommended Crystal Configuration

PARAMETER RECOMMENDED UNIT
Crystal circuit configuration Parallel resonant
Crystal type Fundamental (first harmonic)
Crystal nominal frequency (See TSTPT_6 in the Pin Functions table) 16.667 or 8.333 MHz
Crystal frequency tolerance (including accuracy, temperature, aging, and trim sensitivity) ±200 PPM
Crystal drive level 100 max µW
Crystal equivalent series resistance (ESR) 80 max Ω
Crystal load 12 pF
RS drive resistor (nominal) 100 Ω
RFB feedback resistor (nominal) 1 MΩ
CL1 external crystal load capacitor See Figure 11 pF
CL2 external crystal load capacitor See Figure 11 pF
PCB layout TI recommends a ground isolation ring around the crystal

If an external oscillator is used, then the oscillator output must drive the PLL_REFCLK_I pin on the DLPC2607 ASIC. Leave the PLL_REFCLK_O pins unconnected. An oscillator that provides a spread-spectrum clock reduces EMI.

NOTE

The DLPC2607 device accepts between 0% to –2% spreading (that is, down spreading only) with a modulation frequency between 20 kHz and 65 kHz and a triangular waveform.

Similar to the crystal option, the oscillator input frequency is limited to 16.667 or 8.333 MHz. To configure the DLPC2607 device to accept the 8.333-MHz reference clock option, an external pullup resistor to VCC18 must be applied to the TSTPT (6) pin. To configure the DLPC2607 device to accept the 16.667-MHz reference clock option, leave the TSTPT (6) pin unconnected.

It is assumed that the external crystal or oscillator stabilizes within 50 ms after stable power is applied.