DLPS023C January 2012 – August 2015 DLPC300
Refer to the PDF data sheet for device specific package drawings
Although the DLPC300 requires an array of power supply voltages, (for example, VDD, VDD_PLL, VCC_18, VCC_FLSH, VCC_INTF), there are no restrictions regarding the relative order of power supply sequencing to avoid damaging the DLPC300. This is true for both power-up and power-down scenarios. Similarly, there is no minimum time between powering up or powering down the different supplies feeding the DLPC300. Note, however, that it is not uncommon for there to be power-sequencing requirements for the devices that share the supplies with the DLPC300.
Although there is no risk of damaging the DLPC300 as a result of a given power sequence, from a functional standpoint, there is one specific power-sequencing recommendation to ensure proper operation. In particular, all controller power should be applied and allowed to reach minimum specified voltage levels before RESET is deasserted to ensure proper power-up initialization is performed. All I/O power should remain applied as long as 1-V core power is applied and RESET is deasserted.
Note that when VDD10 core power is applied but I/O power is not applied, additional leakage current may be drawn.
To minimize leakage currents and ensure proper operation, apply the following power up sequence. These steps are numbered in green with a circle around the step number in Figure 17.
To minimize leakage currents and ensure proper operation, apply the following power down sequence. These steps are numbered in red with a square around the step number in Figure 17.
It is assumed that an external power monitor holds the DLPC300 in system reset during power-up. It must do this by driving RESET to a logic-low state. It should continue to assert system reset until all controller voltages have reached minimum specified voltage levels, PARK is asserted high, and input clocks are stable. During this time, most controller outputs are driven to an inactive state and all bidirectional signals are configured as inputs to avoid contention. Controller outputs that are not driven to an inactive state are in the high-impedance state. These include DMD_PWR_EN, LEDDVR_ON, LED_SEL_0, LED_SEL_1, SPICLK, SPIDOUT, and SPICS0. After power is stable and the PLL_REFCLK clock input to the DLPC300 is stable, then RESET should be deactivated (set to a logic high). The DLPC300 then performs a power-up initialization routine that first locks its PLL followed by loading self-configuration data from the external flash. On release of RESET, all DLPC300 I/Os become active. Immediately following the release of RESET, the INIT_BUSY signal is driven high to indicate that the auto-initialization routine is in progress. On completion of the auto-initialization routine, the DLPC300 drives INIT_BUSY low to signal INITIALIZATION DONE.
See Figure 18 for a visualization of this sequence.
The PARK signal is defined to be an early warning signal that should alert the controller 500 µs before dc supply voltages have dropped below specifications. This allows the controller time to park the DMD, ensuring the integrity of future operation. Note that the reference clock should continue to run and RESET should remain deactivated for at least 500 µs after PARK has been deactivated (set to a logic low) to allow the park operation to complete.