DLPS143B July   2018  – October 2020 DLPC3434

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Test Pins and General Control
    2. 5.2 Parallel Port Input
    3. 5.3 DSI Input Data and Clock
    4. 5.4 DMD Reset and Bias Control
    5. 5.5 DMD Sub-LVDS Interface
    6. 5.6 Peripheral Interface
    7. 5.7 GPIO Peripheral Interface
    8. 5.8 Clock and PLL Support
    9. 5.9 Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillator Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
    15. 6.15 Other Timing Requirements
    16. 6.16 DMD Sub-LVDS Interface Switching Characteristics
    17. 6.17 DMD Parking Switching Characteristics
    18. 6.18 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Source Requirements
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 Parallel Interface Data Transfer Format
        3. 7.3.1.3 3D Display
      2. 7.3.2 Device Startup
      3. 7.3.3 SPI Flash
        1. 7.3.3.1 SPI Flash Interface
        2. 7.3.3.2 SPI Flash Programming
      4. 7.3.4 I2C Interface
      5. 7.3.5 Content Adaptive Illumination Control (CAIC)
      6. 7.3.6 Local Area Brightness Boost (LABB)
      7. 7.3.7 3D Glasses Operation
      8. 7.3.8 Test Point Support
      9. 7.3.9 DMD Interface
        1. 7.3.9.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast Park Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PLL Power Layout
      2. 10.1.2 Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3 Unused Pins
      4. 10.1.4 DMD Control and Sub-LVDS Signals
      5. 10.1.5 Layer Changes
      6. 10.1.6 Stubs
      7. 10.1.7 Terminations
      8. 10.1.8 Routing Vias
      9. 10.1.9 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Video Timing Parameter Definitions
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

6.6 Pin Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER(1) TEST CONDITIONS(2) MIN TYP MAX UNIT
VIH High-level input threshold voltage I2C buffer (I/O type 7) 0.7 × VCC_INTF See (4) V
I/O type 1, 2, 3, 6, 8 except pins noted in (5) VCC18 = 1.8 V 1.17 3.6
I/O type 1, 6 for pins noted in (5) VCC18 = 1.8 V 1.3 3.6
I/O type 5, 9, 11 VCC_INTF = 1.8 V 1.17 3.6
I/O type 12, 13 VCC_FLSH = 1.8 V 1.17 3.6
I/O type 5, 9, 11 VCC_INTF = 2.5 V 1.7 3.6
I/O type 12, 13 VCC_FLSH = 2.5 V 1.7 3.6
I/O type 5, 9, 11 VCC_INTF = 3.3 V 2.0 3.6
I/O type 12, 13 VCC_FLSH = 3.3 V 2.0 3.6
VIL Low-level input threshold voltage I2C buffer (I/O type 7) –0.5 0.3 × VCC_INTF V
I/O type 1, 2, 3, 6, 8 except pins noted in (5) VCC18 = 1.8 V –0.3 0.63
I/O type 1, 6 for pins noted in (5) VCC18 = 1.8 V –0.3 0.5
I/O type 5, 9, 11 VCC_INTF = 1.8 V –0.3 0.63
I/O type 12, 13 VCC_FLSH = 1.8 V –0.3 0.63
I/O type 5, 9, 11 VCC_INTF = 2.5 V –0.3 0.7
I/O type 12, 13 VCC_FLSH = 2.5 V –0.3 0.7
I/O type 5, 9, 11 VCC_INTF = 3.3 V –0.3 0.8
I/O type 12, 13 VCC_FLSH = 3.3 V –0.3 0.8
VOH High-level output voltage I/O type 1, 2, 3, 6, 8 VCC18 = 1.8 V 1.35 V
I/O type 5, 9, 11 VCC_INTF = 1.8 V 1.35
I/O type 12, 13 VCC_FLSH = 1.8 V 1.35
I/O type 5, 9, 11 VCC_INTF = 2.5 V 1.7
I/O type 12, 13 VCC_FLSH = 2.5 V 1.7
I/O type 5, 9, 11 VCC_INTF = 3.3 V 2.4
I/O type 12, 13 VCC_FLSH = 3.3 V 2.4
VOL Low-level output voltage I2C buffer (I/O type 7) VCC_INTF > 2 V 0.4 V
I2C buffer (I/O type 7) VCC_INTF < 2 V 0.2 × VCC_INTF
I/O type 1, 2, 3, 6, 8 VCC18 = 1.8 V 0.45
I/O Type 5, 9, 11 VCC_INTF = 1.8 V 0.45
I/O Type 12, 13 VCC_FLSH = 1.8 V 0.45
I/O Type 5, 9, 11 VCC_INTF = 2.5 V 0.7
I/O Type 12, 13 VCC_FLSH = 2.5 V 0.7
I/O Type 5, 9, 11 VCC_INTF = 3.3 V 0.4
I/O Type 12, 13 VCC_FLSH = 3.3 V 0.4
over operating free-air temperature range (unless otherwise noted)
PARAMETER(1) TEST CONDITIONS(2) MIN TYP MAX UNIT
IOH High-level output current(3) I/O type 2, 4 VCC18 = 1.8 V 2 mA
I/O type 5 VCC_INTF = 1.8 V 2
I/O type 1 VCC18 = 1.8 V 3.5
I/O type 9 VCC_INTF = 1.8 V 3.5
I/O type 13 VCC_FLSH = 1.8 V 3.5
I/O type 3 VCC18 = 1.8 V 10.6
I/O type 5 VCC_INTF = 2.5 V 5.4
I/O type 9, 13 VCC_INTF = 2.5 V 10.8
I/O type 13 VCC_FLSH = 2.5 V 10.8
I/O type 5 VCC_INTF = 3.3 V 7.8
I/O type 9 VCC_INTF = 3.3 V 15
I/O type 13 VCC_FLSH = 3.3 V 15
IOL Low-level output current(6) I2C buffer (I/O type 7) 3 mA
I/O type 2, 4 VCC18 = 1.8 V 2.3
I/O type 5 VCC_INTF = 1.8 V 2.3
I/O type 1 VCC18 = 1.8 V 4.6
I/O type 9 VCC_INTF = 1.8 V 4.6
I/O type 13 VCC_FLSH = 1.8 V 4.6
I/O type 3 VCC18 = 1.8 V 13.9
I/O type 5 VCC_INTF = 2.5 V 5.2
I/O type 9 VCC_INTF = 2.5 V 10.4
I/O type 13 VCC_FLSH = 2.5 V 10.4
I/O type 5 VCC_INTF = 3.3 V 4.4
I/O type 9 VCC_INTF = 3.3 V 8.9
I/O type 13 VCC_FLSH = 3.3 V 8.9
over operating free-air temperature range (unless otherwise noted)
PARAMETER(1) TEST CONDITIONS(2) MIN TYP MAX UNIT
IOZ High-impedance leakage current I2C buffer (I/O type 7) VI2C buffer < 0.1 × VCC_INTF or
VI2C buffer > 0.9 × VCC_INTF		 –10 10 µA
I/O type 1, 2, 3, 6, 8, VCC18 = 1.8 V –10 10
I/O Type 5, 9, 11 VCC_INTF = 1.8 V –10 10
I/O Type 12, 13 VCC_FLSH = 1.8 V –10 10
I/O type 5, 9, 11 VCC_INTF = 2.5 V –10 10
I/O Type 12, 13 VCC_FLSH = 2.5 V –10 10
I/O Type 5, 9, 11 VCC_INTF = 3.3 V –10 10
I/O type 12, 13 VCC_FLSH = 3.3 V –10 10
CI Input capacitance (including package) I2C buffer (I/O type 7) 5 pF
I/O type 1, 2, 3, 6, 8 VCC18 = 1.8 V 2.6 3.5
I/O Type 5, 9, 11 VCC_INTF = 1.8 V 2.6 3.5
I/O Type 12, 13 VCC_FLSH = 1.8 V 2.6 3.5
I/O type 5, 9, 11 VCC_INTF = 2.5 V 2.6 3.5
I/O type 12, 13 VCC_FLSH = 2.5 V 2.6 3.5
I/O type 5, 9, 11 VCC_INTF = 3.3 V 2.6 3.5
I/O type 12, 13 VCC_FLSH = 3.3 V 2.6 3.5
sub-LVDS – DMD high speed (I/O type 4) VCC18 = 1.8 V 3
(1) The I/O type refers to the type defined in
(2) Test conditions that define a value for VCC18, VCC_INTF, or VCC_FLSH show the nominal voltage that the specified I/O's supply reference is set to.
(3) At a high level output signal, the given I/O will be able to output at least the minimum current specified.
(4) I/O is high voltage tolerant; that is, if VCC_INTF = 1.8 V, the input is 3.3-V tolerant, and if VCC_INTF = 3.3 V, the input is 5-V tolerant.
(5) Controller pins CMP_OUT, PARKZ, RESETZ, and GPIO_00 through GPIO_19 have slightly varied VIH and VIL range from other 1.8-V I/O.
(6) At a low level output signal, the given I/O will be able to sink at least the minimum current specified.