DLPS038E July   2014  – August 2019 DLPC3430 , DLPC3435

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Typical, Simplified System
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions – Test Pins and General Control
    2.     Pin Functions – Parallel Port Input
    3.     Pin Functions – DSI Input Data and Clock
    4.     Pin Functions – DMD Reset and Bias Control
    5.     Pin Functions – DMD Sub-LVDS Interface
    6.     Pin Functions – Peripheral Interface
    7.     Pin Functions – GPIO Peripheral Interface
    8.     Pin Functions – Clock and PLL Support
    9.     Pin Functions – Power and Ground
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillator Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 BT656 Interface General Timing Requirements
    15. 6.15 DSI Host Timing Requirements
    16. 6.16 Flash Interface Timing Requirements
    17. 6.17 Other Timing Requirements
    18. 6.18 DMD Sub-LVDS Interface Switching Characteristics
    19. 6.19 DMD Parking Switching Characteristics
    20. 6.20 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Source Requirements
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 3D Display
        3. 7.3.1.3 Parallel Interface
          1. 7.3.1.3.1 PDATA Bus – Parallel Interface Bit Mapping Modes
        4. 7.3.1.4 DSI Interface
      2. 7.3.2 Device Startup
      3. 7.3.3 SPI Flash
        1. 7.3.3.1 SPI Flash Interface
        2. 7.3.3.2 SPI Flash Programming
      4. 7.3.4 I2C Interface
      5. 7.3.5 Content Adaptive Illumination Control (CAIC)
      6. 7.3.6 Local Area Brightness Boost (LABB)
      7. 7.3.7 3D Glasses Operation
      8. 7.3.8 Test Point Support
      9. 7.3.9 DMD Interface
        1. 7.3.9.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast Park Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  PLL Power Layout
      2. 10.1.2  Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3  DSI Interface Layout
      4. 10.1.4  Unused Pins
      5. 10.1.5  DMD Control and Sub-LVDS Signals
      6. 10.1.6  Layer Changes
      7. 10.1.7  Stubs
      8. 10.1.8  Terminations
      9. 10.1.9  Routing Vias
      10. 10.1.10 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Video Timing Parameter Definitions
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

3D Glasses Operation

When using 3D glasses (with 3D video input and appropriate software support), the controller outputs sync information to align the left eye and right eye shuttering in the glasses with the displayed DMD image frames. 3D glasses typically use either Infrared (IR) transmission or DLP Link ™technology to achieve this synchronization.

One glasses type uses an IR transmitter on the system PCB to send an IR sync signal to an IR receiver in the glasses. In this case DLPC34xx controller output signal GPIO_04 can be used to cause the IR transmitter to send an IR sync signal to the glasses. Figure 11 shows the timing sequence for the GPIO_04 signal.

The second type of glasses relies on sync information that is encoded into the light being output from the projection lens. This approach uses the DLP Link feature for 3D video. Many 3D glasses from different suppliers have been built using this method. The advantage of using the DLP Link feature is that it takes advantage of existing projector hardware to transmit the sync information to the glasses. This method may give an advantage in cost, size and power savings in the projector.

When using DLP Link technology, one light pulse per DMD frame is output from the projection lens while the glasses have both shutters closed. To achieve this, the DLPC34xx tells the DLPAxxxx when to turn on the illumination source (typically LEDs or lasers) so that an encoded light pulse is output once per DMD frame. Because the shutters in the glasses are both off when the pulse is sent, the projector illumination source is also off except when the light is sent to create the pulse. The pulses may use any color; however, due to the transmission property of the eye-glass LCD shutter lenses and the sensitivity of the white-light sensor used on the eye-glasses, it is highly recommended that blue is not used for pulses. Red pulses are the recommended color to use. Figure 24 shows 3D timing information. Figure 25 and Table 10 show the timing for the light pulses when using the DLP Link feature.

DLPC3430 DLPC3435 input_source_timing_dlps000.gif
(1) Left = 1, Right = 0
(2) 3DR must toggle 1 ms before VSYNC
t1: both shutters turned off
t2: next shutter turned on
Figure 24. 3D Display Left and Right Frame and Signal Timing
DLPC3430 DLPC3435 td_3d_dlp_link_pulse_dlps000.gif
The time offset of DLP Link pulses at the end of a subframe alternates between B and B+D where D is the delta offset.
Figure 25. 3D DLP Link Pulse Timing
HDMI Source Frame Rate (Hz) DLPC34xx Input Frame Rate (Hz) A
(µs)
B
(µs)
C
(µs)
D
(µs)
E
(µs)
49.0 98 20 - 32
(31.8 nominal)
>500 >622 128 - 163
(161.6 nominal)
>2000
50.0 100 20 - 32
(31.2 nominal)
>500 >658 128 - 163
(158.4 nominal)
>2000
51.0 102 20 - 32
(30.6 nominal)
>500 >655 128 - 163
(155.3 nominal)
>2000
59.0 118 20 - 32
(26.4 nominal)
>500 >634 128 - 163
(134.2 nominal)
>2000
60.0 120 20 - 32
(26.0 nominal)
>500 >632 128 - 163
(132.0 nominal)
>2000
61.0 122 20 - 32
(25.6 nominal)
>500 >630 128 - 163
(129.8 nominal)
>2000
Timing parameter C is always the sum of B+D.