10.1.3 DSI Interface Layout
Follow these PCB layout guidelines for the DSI LVDS interface to ensure proper DSI operation.
- Route the differential clock and data lines to match 50-Ω single-ended and 100-Ω differential impedance.
- The length of dp and dn should be matched. If that is not possible, ensure that dp is only slightly longer than dn (delta delay not to exceed 8-10 ps), especially for the clock-lane. This is to prevent propagation on the clock lane during the HS to LP transition.
- No thru-hole vias permitted on high-speed traces.
- Create trace routes on top or bottom layers preferably.
- Must have a ground reference plane.
- Avoid power plane transitions in upper or lower layers.
- Avoid using SMD (surface mount device) resistors larger than 0402. If resistors are used in the traces, ensure that the layer below has a void.
- No thru-hole SMA (SubMiniature version A) connectors.
- Minimize trace length as much as possible.
- Perform signal integrity simulations to ensure board performance.