The parallel interface complies with standard graphics interface protocol, which includes the signals listed in Table 5.
|PDATA||24-bit data bus|
|PDM_CVS_TE||parallel data mask (optional)|
VSYNC_WE must remain active at all times when using parallel RGB mode. When this signal is no longer active, the display sequencer stops and causes the LEDs to turn off.
The active edge of both sync signals are variable. Parallel Interface Frame Timing Requirements shows the relationship of these signals.
An optional parallel data mask signal (PDM_CVS_TE) allows periodic frame updates to be stopped without losing the displayed image. When active, PDM_CVS_TE acts as a data mask and does not allow the source image to be propagated to the display. A programmable PDM polarity parameter determines if it is active high or active low. PDM_CVS_TE defaults to active high. To disable the data mask function, tie PDM_CVS_TE to a logic low signal. PDM_CVS_TE must only change during vertical blanking.
The parallel interface supports six data transfer formats. They are as follows:
The PDATA Bus – Parallel Interface Bit Mapping Modes section shows the required PDATA(23:0) bus mapping for these six data transfer formats.