DLPS038E July   2014  – August 2019 DLPC3430 , DLPC3435

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Typical, Simplified System
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions – Test Pins and General Control
    2.     Pin Functions – Parallel Port Input
    3.     Pin Functions – DSI Input Data and Clock
    4.     Pin Functions – DMD Reset and Bias Control
    5.     Pin Functions – DMD Sub-LVDS Interface
    6.     Pin Functions – Peripheral Interface
    7.     Pin Functions – GPIO Peripheral Interface
    8.     Pin Functions – Clock and PLL Support
    9.     Pin Functions – Power and Ground
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillator Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 BT656 Interface General Timing Requirements
    15. 6.15 DSI Host Timing Requirements
    16. 6.16 Flash Interface Timing Requirements
    17. 6.17 Other Timing Requirements
    18. 6.18 DMD Sub-LVDS Interface Switching Characteristics
    19. 6.19 DMD Parking Switching Characteristics
    20. 6.20 Chipset Component Usage Specification
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Source Requirements
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 3D Display
        3. 7.3.1.3 Parallel Interface
          1. 7.3.1.3.1 PDATA Bus – Parallel Interface Bit Mapping Modes
        4. 7.3.1.4 DSI Interface
      2. 7.3.2 Device Startup
      3. 7.3.3 SPI Flash
        1. 7.3.3.1 SPI Flash Interface
        2. 7.3.3.2 SPI Flash Programming
      4. 7.3.4 I2C Interface
      5. 7.3.5 Content Adaptive Illumination Control (CAIC)
      6. 7.3.6 Local Area Brightness Boost (LABB)
      7. 7.3.7 3D Glasses Operation
      8. 7.3.8 Test Point Support
      9. 7.3.9 DMD Interface
        1. 7.3.9.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast Park Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  PLL Power Layout
      2. 10.1.2  Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3  DSI Interface Layout
      4. 10.1.4  Unused Pins
      5. 10.1.5  DMD Control and Sub-LVDS Signals
      6. 10.1.6  Layer Changes
      7. 10.1.7  Stubs
      8. 10.1.8  Terminations
      9. 10.1.9  Routing Vias
      10. 10.1.10 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Video Timing Parameter Definitions
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

Power Electrical Characteristics(4)(5)(6)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX(2) UNIT
I(VDD) + I(VDD_PLLM) + I(VDD_PLLD) 1.1V rails Frame rate = 60 Hz 111 160 mA
Frame rate = 120 Hz 132 196
Frame rate = 240 Hz 179 295
I(VDD_PLLM) MCG PLL 1.1-V current(3) Frame rate = 60 Hz 6 mA
Frame rate = 120 Hz 6
Frame rate = 240 Hz 6
I(VDD_PLLD) DCG PLL 1.1-V current(3) Frame rate = 60 Hz 6 mA
Frame rate = 120 Hz 6
Frame rate = 240 Hz 6
I(VCC18) All 1.8-V I/O current: (1.8-V power supply for all I/O other than the host or parallel interface and the SPI flash interface) Frame rate = 60 Hz 27 36 mA
Frame rate = 120 Hz 27 36
Frame rate = 240 Hz 27 36
I(VCC_INTF) Host or parallel interface I/O current: 1.8 to 3.3 V (includes IIC0, PDATA, video syncs, and HOST_IRQ pins)(3) Frame rate = 60 Hz 2 mA
Frame rate = 120 Hz 2
Frame rate = 240 Hz 2
I(VCC_FLSH) Flash interface I/O current:1.8 to 3.3 V(3) Frame rate = 60 Hz 1 mA
Frame rate = 120 Hz 1
Frame rate = 240 Hz 1
If measured on a system, typical PVT (process, voltage, and temperature) conditions (i.e. nominal process, typical voltage, and 25°C nominal ambient temperature) and various input images were used.
Measured on a system with worst case PVT condition(s) (i.e. corner process, high voltage, and high temperature of 65°C) and white noise input image.
This rail was not measured due to board limitations. Simulation values are used instead. Simulations assume 12.5% activity factor, 30% clock gating on appropriate domains, and mixed SVT (standard threshold voltage) or HVT (high threshold voltage) cells.
For the measured cases, all pins using 1.1 V were tied together (including VDDLP12), and programmable host and flash I/O are at the minimum nominal voltage (that is 1.8 V).
Input image is 854 × 480 (WVGA) 24-bits using reduced VESA timings on the parallel interface at the frame rate shown with the 0.2-inch WVGA (DLP2010) DMD. The controller has the CAIC and LABB algorithms turned off.
The measured values do not take into account software updates or customer changes that may affect power performance.