The DLPC34xx controller requires an external SPI serial flash memory device to store the firmware. Follow the below guidelines and requirements in addition to the requirements listed in the Flash Interface Timing Requirements section.
The controller supports a maximum flash size of 64 Mb (8 MB). See Table 9 for example compatible flash options. The minimum required flash size depends on the size of the utilized firmware. The firmware size depends upon a variety of factors including the number of sequences, lookup tables, and splash images.
The DLPC34xx controller uses a single SPI interface that complies to industry standard SPI flash protocol. The device will begin accessing the flash at a nominal 1.42 MHz frequency before running at a nominal 30 MHz rate. The flash device must support these rates.
The controller has two independent SPI chip select (CS) control lines. Ensure the flash device's chip select pin is connected to SPI0_CSZ0 as the controller's boot routine is executed from the device connected to chip select zero. The boot routine uploads program code from flash memory to program memory then transfers control to an auto-initialization routine within program memory.
|SPI interface width||Single|
|SPI polarity and phase settings||SPI mode 0|
|Fast READ addressing||Auto-incrementing|
|Programming mode||Page mode|
|Page size||256 B|
|Sector size||4 KB sector|
|Block protection bits||0 = Disabled|
|Status register bit(0)||Write in progress (WIP), also called flash busy|
|Status register bit(1)||Write enable latch (WEN)|
|Status register bits(6:2)||A value of 0 disables programming protection|
|Status register bit(7)||Status register write protect (SRWP)|
|Status register bits(15:8)
(that is expansion status byte)
|Because the DLPC34xx controller supports only single-byte status register R/W command execution, it may not be compatible with flash devices that contain an expansion status byte. However, as long as the expansion status byte is considered optional in the byte 3 position and any write protection control in this expansion status byte defaults to unprotected, then the flash device is likely compatible with the DLPC34xx.|
The DLPC34xx controller is intended to support flash devices with program protection defaults of either enabled or disabled. The controller assumes the default is enabled and proceeds to disable any program protection as part of the boot process.
The DLPC34xx issues these commands during the boot process:
Prior to each program or erase instruction, the DLPC34xx controller issues similar commands:
Note that the flash device automatically clears the write enable status after each program and erase instruction.
|SPI FLASH COMMAND|| BYTE 1
|BYTE 2||BYTE 3||BYTE 4||BYTE 5||BYTE 6|
|Fast READ (1 Output)||0x0B||ADDRS(0)||ADDRS(1)||ADDRS(2)||dummy||DATA(0)(1)|
|Sector erase (4 KB)||0x20||ADDRS(0)||ADDRS(1)||ADDRS(2)|
|SPI FLASH TIMING PARAMETER||SYMBOL||ALTERNATE SYMBOL||MIN||MAX||UNIT|
|Access frequency (all commands)||FR||fC||≤1.4||≥ 30.1||MHz|
|Chip select high time (also called chip select deselect time)||tSHSL||tCSH||≤ 200||ns|
|Output hold time||tCLQX||tHO||≥ 0||ns|
|Clock low to output valid time||tCLQV||tV||≤ 11||ns|
|Data in set-up time||tDVCH||tDSU||≤ 5||ns|
|Data in hold time||tCHDX||tDH||≤ 5||ns|
In order for the DLPC34xx controller to support 1.8-V, 2.5-V, or 3.3-V serial flash devices, the VCC_FLSH pin must be supplied with the corresponding voltage. Table 9 contains a list of validated 1.8-V, 2.5-V, or 3.3-V compatible SPI serial flash devices supported by the DLPC34xx controller.
|DENSITY (Mb)||VENDOR||PART NUMBER||PACKAGE SIZE|
|1.8-V COMPATIBLE DEVICES|
|4 Mb||Winbond||W25Q40BWUXIG||2 × 3 mm USON|
|4 Mb||Macronix||MX25U4033EBAI-12G||1.43 × 1.94 mm WLCSP|
|8 Mb||Macronix||MX25U8033EBAI-12G||1.68 × 1.99 mm WLCSP|
|2.5- OR 3.3-V COMPATIBLE DEVICES|
|16 Mb||Winbond||W25Q16CLZPIG||5 × 6 mm WSON|