DLPS110B April   2018  – June 2019 DLPC3470

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Standalone System
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions – Board Level Test, Debug, and Initialization
    2.     Pin Functions – Parallel Port Input Data and Control
    3.     Pin Functions - DSI Input Data and Clock
    4.     Pin Functions – DMD Reset and Bias Control
    5.     Pin Functions – DMD Sub-LVDS Interface
    6.     Pin Functions – Peripheral Interface
    7.     Pin Functions – GPIO Peripheral Interface
    8.     Pin Functions – Clock and PLL Support
    9.     Pin Functions – Power and Ground
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics over Recommended Operating Conditions
    6. 6.6  Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Characteristics
    8. 6.8  High-Speed Sub-LVDS Electrical Characteristics
    9. 6.9  Low-Speed SDR Electrical Characteristics
    10. 6.10 System Oscillators Timing Requirements
    11. 6.11 Power-Up and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 BT656 Interface General Timing Requirements
    15. 6.15 Flash Interface Timing Requirements
  7. Parameter Measurement Information
    1. 7.1 HOST_IRQ Usage Model
    2. 7.2 Input Source
      1. 7.2.1 Input Source - Frame Rates and 3-D Display Orientation
      2. 7.2.2 Parallel Interface Supports Six Data Transfer Formats
        1. 7.2.2.1 PDATA Bus – Parallel Interface Bit Mapping Modes
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pattern Display
        1. 8.3.1.1 External Pattern Mode
          1. 8.3.1.1.1 8-bit Monochrome Patterns
          2. 8.3.1.1.2 1-Bit Monochrome Patterns
        2. 8.3.1.2 Internal Pattern Mode
          1. 8.3.1.2.1 Free Running Mode
          2. 8.3.1.2.2 Trigger In Mode
      2. 8.3.2 Interface Timing Requirements
        1. 8.3.2.1  Parallel Interface
        2. 8.3.2.2  Serial Flash Interface
        3. 8.3.2.3  Serial Flash Programming
        4. 8.3.2.4  SPI Signal Routing
        5. 8.3.2.5  I2C Interface Performance
        6. 8.3.2.6  Content-Adaptive Illumination Control
        7. 8.3.2.7  Local Area Brightness Boost
        8. 8.3.2.8  3-D Glasses Operation
        9. 8.3.2.9  DMD (Sub-LVDS) Interface
        10. 8.3.2.10 DLPC3470 controller System Design Consideration – Application Notes
        11. 8.3.2.11 Calibration and Debug Support
        12. 8.3.2.12 DMD Interface Considerations
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 3D Depth Scanner Using External Pattern Streaming Mode
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 3D Depth Scanner Using Internal Pattern Streaming Mode
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 System Power-Up and Power-Down Sequence
    2. 10.2 DLPC3470 controller Power-Up Initialization Sequence
    3. 10.3 DMD Fast PARK Control (PARKZ)
    4. 10.4 Hot Plug Usage
    5. 10.5 Maximum Signal Transition Time
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1  PCB Layout Guidelines for Internal ASIC PLL Power
      2. 11.1.2  DLPC3470 controller Reference Clock
        1. 11.1.2.1 Recommended Crystal Oscillator Configuration
      3. 11.1.3  General PCB Recommendations
      4. 11.1.4  General Handling Guidelines for Unused CMOS-Type Pins
      5. 11.1.5  Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
      6. 11.1.6  Number of Layer Changes
      7. 11.1.7  Stubs
      8. 11.1.8  Terminations
      9. 11.1.9  Routing Vias
      10. 11.1.10 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Device Nomenclature
        1. 12.1.2.1 Device Markings
      3. 12.1.3 Video Timing Parameter Definitions
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Display and Light Controller for DLP2010 and DLP2010NIR (0.2 WVGA) TRP DMD
  • Display Features
    • Supports Input Image Sizes up to 720p
    • Input Frame Rates to 120 Hz (2D and 3D)
    • 24-Bit, Input Pixel Interface Support:
      • Parallel or BT656, Interface Protocols
      • Pixel Clock up to 150 MHz
    • Image Processing - IntelliBright™ Algorithms , Image Resizing, 1D Keystone, CCA, Programmable Degamma
  • Light Control Features:
    • Pattern display optimized for machine vision and digital exposure
    • Flexible internal (1D) and external (2D) pattern streaming modes
      • Programmable exposure times
      • High speed pattern rates up to 2500 Hz (1-bit) and 360Hz (8-bit)
    • Programmable 2D Static Patterns via Splash
    • Internal Pattern streaming mode enables simplified system design
      • Eliminates the need for Video interface
      • Store >1000 patterns in the flash memory
    • Flexible trigger signals for camera/sensor synchronization
      • One configurable input trigger
      • Two configurable output triggers
  • System Features:
    • I2C Control of Device Configuration
    • Programmable Splash Screens
    • Programmable LED Current Control
    • Auto DMD Parking at Power Down