DLPS074 February 2017 DLPC4422
Following system power-up, the DLPC4422 device performs a power-up initialization routine that defaults the device to it’s normal power mode, in which ARM9-related clocks are enabled at their full rate and associated resets are released. Most other clocks default to disabled state with associated resets asserted until released by the processor. In addition, the default for system power gating enables all power. These same defaults are also applied as part of all system reset events (Watch Dog timer timeout, Lamp Strike reset, etc) that occur without removing or cycling power, with the possible exception of power for the LVDS I/O and internal DRAM. For an extended reset condition, the OEM is expected to place the ASIC in Low Power mode prior to reset, in which case the 1.8-V power for the LVDS I/O and internal DRAM will be disabled. When this reset is release, the 1.8-V power won’t be enabled until the ARM9 has been initialized and is executing it’s system initialization routines.
Following power-up or system reset initialization, the ARM9 boots from an external flash memory after which it enables the 1.8-V power (from the DLPA100), enables the rest of the ASIC clocks, and initializes the internal DRAM. Once system initialization is complete the Application software determines if and when to enter low power mode.