10.1.1 PCB Layout Guidelines for Internal ASIC Power
TI recommends the following guidelines to achieve desired ASIC performance relative to internal PLLs:
- The DLPC4422 device contains four PLLs (PLLM1, PLLM2, PLLD & PLLS), each of which have a dedicated 1.1-V digital supply, and three (PLLM1, PLLM2 & PLLD) which have a dedicated 1.8-V analog supply. It is important to have filtering on the supply pins that covers a broad frequency range. Each 1.1-V PLL supply pin should have individual high frequency filtering in the form of a ferrite bead and a 0.1 µF ceramic capacitor. These components should be located very close to the individual PLL supply balls. The impedance of the ferrite bead should be much greater than that of the capacitor at frequencies above 10 MHz. The 1.1-V to the PLL supply pins should also have low frequency filtering in the form of an RC filter. This filter can be common to all the PLLs. The voltage drop across the resistor is limited by the 1.1-V regulator tolerance and the DLPC4422 device voltage tolerance. A resistance of 0.36 Ω and a 100 µF ceramic are recommended.
- The analog 1.8-V PLL power pins should have a similar filter topology as the 1.1 V. In addition, TI recommends that the 1.8-V be generated with a dedicated linear regulator.
- When designing the overall supply filter network, care must be taken to ensure no resonance occurs. Particular care must be taken around the 1- to 2-MHz band, as this coincides with the PLL natural loop frequency.
Figure 13. PLL Filter Layout
High frequency decoupling is required for both 1.1-V and 1.8-V PLL supplies and should be provided as close as possible to each of the PLL supply package pins. TI recommends placing decoupling capacitors under the package on the opposite side of the board. Use high quality, low-ESR, monolithic, surface mount capacitors. Typically 0.1µF for each PLL supply should be sufficient. The length of a connecting trace increases the parasitic inductance of the mounting and thus, where possible, there should be no trace, allowing the via to butt up against the land itself. Additionally, the connecting trace should be made as wide as possible. Further improvement can be made by placing vias to the side of the capacitor lands or doubling the number of vias.
The location of bulk decoupling depends on the system design.