DLPS074 February 2017 DLPC4422
Although the DLPC4422 controller requires an array of power supply voltages (1.1 V, 1.8 V, 3.3 V), there are no restrictions regarding the relative order of power supply sequencing. This is true for both power-up and power-down scenarios. Similarly, there is no minimum time between powering-up or powering-down the different supplies feeding the DLPC4422 controller. However, note that it is not uncommon for there to be power sequencing requirements for the devices that share the supplies with the DLPC4422 controller.
It is assumed that all DLPC4422 device power-up sequencing is handled by external hardware. It is also assumed that an external power monitor will hold the DLPC4422 device in system reset during power-up (i.e. POSENSE = 0). During this time all DLPC4422 device I/O will be tri-stated. The master PLL (PLLM1) is released from reset upon the low to high transition of POSENSE but the DLPC4422 device keeps the rest of the device in reset for an additional 60 ms to allow the PLL to lock and stabilize its outputs. After this 60 ms delay the ARM-9 related internal resets will be de-asserted causing the microprocessor to begin its boot-up routine.