184.108.40.206 System Reset Operation
Immediately following any type of system reset (Power-up reset, PWRGOOD reset, watchdog timer timeout, lamp-strike reset, etc), the DLPC4422 device shall automatically return to NORMAL power mode and return to the following state:
- All GPIO will tri-state.
- The Master PLL will remain active (it is reset only after a power-up reset sequence) and most of the derived clocks are active. However, only those resets associated with the ARM9 processor and its peripherals will be released (The ARM9 is responsible for releasing all other resets).
- ARM9 associated clocks default to their full clock rates. (Boot-up is a full speed)
- All front end clocks derived are disabled.
- The PLL feeding the LVDS DMD I/F (PLLD) defaults to its power-down mode and all derived clocks are inactive with corresponding resets asserted (The ARM9 is responsible for enabling these clocks and releasing associated resets).
- LVDS I/O defaults to its power-down mode with outputs tri-stated.
- All resets output by the DLPC4422 device remain asserted until released by the ARM9. (after boot-up)
- The ARM9 processor boots-up from external flash.
When the ARM9 boots-up, the ARM9 API:
- Configures the programmable DDR Clock Generator (DCG) clock rates (i.e. the DMD LVDS I/F rate)
- Enables the DCG PLL (PLLD) while holding divider logic in reset
- When the DCG PLL locks, ARM9 software sets DMD clock rates
- API software then releases DCG divider logic resets, which in turn, enable all derived DCG clocks
- Release external resets
Application software then typically waits for a wake-up command (through the soft power switch on the projector) from the end user. When the projector is requested to wake-up, the software places the ASIC back in normal mode, re-initialize clocks, and resets as required.