DLPS117B
July 2018 – October 2020
DLPC6421
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
System Oscillators Timing Requirements
6.7
Test and Reset Timing Requirements
6.8
JTAG Interface: I/O Boundary Scan Application Timing Requirements
6.9
Port 1 Input Pixel Timing Requirements
6.10
DMD LVDS Interface Timing Requirements
6.11
Synchronous Serial Port (SSP) Interface Timing Requirements
6.12
Programmable Output Clocks Switching Characteristics
6.13
Synchronous Serial Port Interface (SSP) Switching Characteristics
6.14
JTAG Interface: I/O Boundary Scan Application Switching Characteristics
7
Detailed Description
7.1
Overview
7.2
Feature Description
7.2.1
System Reset Operation
7.2.1.1
Power-up Reset Operation
7.2.1.2
System Reset Operation
7.2.2
Spread Spectrum Clock Generator Support
7.2.3
GPIO Interface
7.2.4
Source Input Blanking
7.2.5
Video Graphics Processing Delay
7.2.6
Program Memory Flash
7.2.7
Calibration and Debug Support
7.2.8
Board Level Test Support
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.1.1
Recommended MOSC Crystal Oscillator Configuration
8.2.2
Detailed Design Procedure
8.2.3
General Handling Guidelines for Unused CMOS-type Pins
9
Power Supply Recommendations
9.1
System Power Regulations
9.2
System Power-Up Sequence
9.3
Power-On Sense (POSENSE) Support
9.4
System Environment and Defaults
9.4.1
DLPC6421 System Power-Up and Reset Default Conditions
9.4.2
1.1-V System Power
9.4.3
1.8-V System Power
9.4.4
3.3-V System Power
9.4.5
Power Good (PWRGOOD) Support
9.4.6
I2C BUSY (I2C_BUSY)
9.4.7
5V Tolerant Support
10
Layout
10.1
Layout Guidelines
10.1.1
PCB Layout Guidelines for Internal DLPC6421 Power
10.1.2
DMD Interface Considerations
10.1.3
Layout Example
10.1.4
Thermal Considerations
11
Device and Documentation Support
11.1
Device Support
11.1.1
Video Timing Parameter Definitions
11.1.2
Device Markings
11.1.2.1
Device Marking Description
11.2
Documentation Support
11.2.1
Related Documentation
11.3
Support Resources
11.4
Trademarks
11.5
Electrostatic Discharge Caution
11.6
Glossary
12
Mechanical, Packaging, and Orderable Information
12.1
Package Option Addendum
12.1.1
Packaging Information
Package Options
Mechanical Data (Package|Pins)
ZPC|516
MPBGAJ0
Thermal pad, mechanical data (Package|Pins)
Orderable Information
dlps117b_oa
1
Features
Dual DLP controller support for up to 4K ultra high definition (UHD) resolution display using
DLP470TP
digital micromirror device (DMD)
Up to 4K at 60 Hz
Up to 240 Hz at 1080p
Up to 120 Hz (3D) at 1080p
Provides one 60-bit input pixel interface:
RGB data format
10 Bits per color
Pixel clock support up to 160 MHz for 60-bit
High-speed, low-voltage differential signaling (LVDS) DMD interface
Microprocessor peripherals
Three I
2
C ports, one UART port and one SSP port
One USB 1.1 slave port
Image processing
Multiple image processing algorithms
Frame rate conversion
Color coordinate adjustment
Programmable color space conversion
Programmable degamma and splash
Integrated support for 3-D display
1-D keystone correction
Integrated clock generation circuitry
Operates on a single 20-MHz crystal
Integrated spread spectrum clocking
External memory support
Parallel flash for microprocessor and PWM sequence
516-pin plastic ball grid array package
Supports LED systems