TI recommends the following guidelines to achieve desired DLPC6421 performance relative to internal PLLs:
- The DLPC6421 device contains four PLL pins (PLLM1, PLLM2, PLLD , and PLLS),
each of which have a dedicated 1.1-V digital supply, and three of which
(PLLM1, PLLM2, and PLLD) have a dedicated 1.8-V analog supply. It is
important to filter the supply pins that cover a broad frequency range. Use
a ferrite bead and a 0.1-µF ceramic capacitor to create the filter for each
1.1-V PLL supply pin . Place these components very close to the individual
PLL supply balls. Ensure that the impedance of the ferrite bead is much
greater than that of the capacitor at frequencies above 10 MHz. Ensure that
the 1.1-V to the PLL supply pins have a low-frequency RC filter. This
low-frequency filter can be common to all the PLLs. The controller limits
the voltage drop across the resistor by the 1.1-V regulator tolerance and
the controller voltage tolerance. A resistance of 0.36 Ω and a 100 µF
ceramic are recommended.
- Use a similar filter topology fro the analog 1.8-V PLL power pins. Use a
dedicated linear regulator to generate the 1.8-V power.
- When designing the overall supply filter network, ensure that no resonance
occurs especially when operating in the 1-MHz to 2-MHz frequency band, as
this coincides with the PLL natural loop frequency.
Figure 10-1 PLL Filter Layout
High frequency decoupling is required for both 1.1-V and 1.8-V PLL supplies and should be provided as close as possible to each of the PLL supply package pins. TI recommends placing decoupling capacitors under the package on the opposite side of the board. Use high quality, low-ESR, monolithic, surface mount capacitors. Typically 0.1µF for each PLL supply should be sufficient. The length of a connecting trace increases the parasitic inductance of the mounting and thus, where possible, there should be no trace, allowing the via to butt up against the land itself. Additionally, the connecting trace should be made as wide as possible. Further improvement can be made by placing vias to the side of the capacitor lands or doubling the number of vias.
The location of bulk decoupling depends on the system design.