DLPS117B July   2018  – October 2020 DLPC6421


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  System Oscillators Timing Requirements
    7. 6.7  Test and Reset Timing Requirements
    8. 6.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 6.9  Port 1 Input Pixel Timing Requirements
    10. 6.10 DMD LVDS Interface Timing Requirements
    11. 6.11 Synchronous Serial Port (SSP) Interface Timing Requirements
    12. 6.12 Programmable Output Clocks Switching Characteristics
    13. 6.13 Synchronous Serial Port Interface (SSP) Switching Characteristics
    14. 6.14 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1 System Reset Operation
        1. Power-up Reset Operation
        2. System Reset Operation
      2. 7.2.2 Spread Spectrum Clock Generator Support
      3. 7.2.3 GPIO Interface
      4. 7.2.4 Source Input Blanking
      5. 7.2.5 Video Graphics Processing Delay
      6. 7.2.6 Program Memory Flash
      7. 7.2.7 Calibration and Debug Support
      8. 7.2.8 Board Level Test Support
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. Recommended MOSC Crystal Oscillator Configuration
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 General Handling Guidelines for Unused CMOS-type Pins
  9. Power Supply Recommendations
    1. 9.1 System Power Regulations
    2. 9.2 System Power-Up Sequence
    3. 9.3 Power-On Sense (POSENSE) Support
    4. 9.4 System Environment and Defaults
      1. 9.4.1 DLPC6421 System Power-Up and Reset Default Conditions
      2. 9.4.2 1.1-V System Power
      3. 9.4.3 1.8-V System Power
      4. 9.4.4 3.3-V System Power
      5. 9.4.5 Power Good (PWRGOOD) Support
      6. 9.4.6 I2C BUSY (I2C_BUSY)
      7. 9.4.7 5V Tolerant Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout Guidelines for Internal DLPC6421 Power
      2. 10.1.2 DMD Interface Considerations
      3. 10.1.3 Layout Example
      4. 10.1.4 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Video Timing Parameter Definitions
      2. 11.1.2 Device Markings
        1. Device Marking Description
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

DMD Interface Considerations

High speed interface waveform quality and timing on the DLPC6421 device (i.e. the LVDS DMD interface) is dependent on the total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus ensuring positive timing margin requires attention to many factors.

As an example, DMD Interface system timing margin can be calculated as follows:

  • Setup Margin = (DLPC6421 output setup) – (DMD input setup) – (PCB routing mismatch) – (PCB SI degradation)
  • Hold-time Margin = (DLPC6421 output hold) – (DMD input hold) – (PCB routing mismatch) – (PCB SI degradation)

Where PCB SI degradation is signal integrity degradation due to PCB effects, which include simultaneously switching output (SSO) noise, cross-talk and inter-symbol interference (ISI) noise. The DLPC6421 device I/O timing parameters as well as DMD I/O timing parameters can be easily found in their corresponding datasheets. Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. However, PCB SI degradation is not so straight forward.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design guidelines are provided as a reference of an interconnect system that satisfies both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Variation from these recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab measurements

PDB Design

Configuration Asymmetric dual stripline
Etch thickness 1.0 oz copper (1.2 mil)
Flex etch thickness 0.5 oz copper (0.6 mil)
Single-ended signal impedance 50 Ω (± 10%)
Differential signal impedance 100 Ω differential (± 10%)

PCB Stackup

Reference plane 1 is assumed to be a ground plane for proper return path.

Reference plane 2 is assumed to be the I/O power plane or ground

Dielectric FR4, (Er) 4.2 (nominal)
Signal trace distance to reference plane 1 (H1) 5.0 mil (nominal)
Signal trace distance to reference plane 2 (H2) 34.2 mil (nominal)
GUID-20201009-CA0I-LSMG-K0ZZ-ZZHN3PLMXVRJ-low.gif Figure 10-2 PCB Stackup Geometries
Table 10-1 General PCB Routing (Applies to All Corresponding PCB Signals)
Line width (W)(1) Escape Routing in Ball Field 4 (0.1) 4 (0.1) mil (mm)
PCB Etch Data or Control 7 (0.18) 4.25 (0.11) mil (mm)
PCB Etch Clocks 7 (0.18) 4.25 (0.11) mil (mm)
Minimum Line spacing to other signals (S) Escape Routing in Ball Field 4 (0.1) 4 (0.1) mil (mm)
PCB Etch Data or Control 10 (0.25) 20 (0.51) mil (mm)
PCB Etch Clocks 20 (0.51) 20 (0.51) mil (mm)
Line width is expected to be adjusted to achieve impedance requirements
Table 10-2 DMD I/F, PCB Interconnect Length Matching Requirements(1)(2)
DMD (LVDS) SCA_P,SCA_N, DDA_P(15:0), DDA_N(15:0) DCKA_P, DCKA_N ±150 (±3.81) mil (mm)
DMD (LVDS) SCB_P,SCB_N, DDB_P(15:0), DDB_N(15:0) DCKB_P, DCKB_N ±150 (±3.81) mil (mm)
These values apply to the PCB routing only. They do not include any internal package routing mismatch associated with the DLPC6421 controller or the DMD. Additional margin can be attained if internal DLPC6421 package skew is taken into account.
To minimize EMI radiation, serpentine routes added to facilitate matching should be implemented on signal layers only, and between reference planes.

Number of layer changes:

  • Single ended signals: Minimize
  • Differential signals: Individual differential pairs can be routed on different layers but the signals of a given pair should not change layers.

Termination requirements:

  • DMD Interface: None, the DMD receiver is differentially terminated to 100 ohm internally

    Connector (DMD-LVDS I/F bus only) - High Speed Connectors that meet the following requirements should be used:

    ● Differential Crosstalk <5 %
    ● Differential Impedance 75-125 ohms

Routing requirements for right angle connectors:

When using right angle connectors, P-N pairs should be routed in same row to minimize delay mismatch.

When using right angle connectors, propagation delay difference for each row should be accounted for on associated PCB etch lengths.