DLPS117B July 2018 – October 2020 DLPC6421
High speed interface waveform quality and timing on the DLPC6421 device (i.e. the LVDS DMD interface) is dependent on the total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus ensuring positive timing margin requires attention to many factors.
As an example, DMD Interface system timing margin can be calculated as follows:
Where PCB SI degradation is signal integrity degradation due to PCB effects, which include simultaneously switching output (SSO) noise, cross-talk and inter-symbol interference (ISI) noise. The DLPC6421 device I/O timing parameters as well as DMD I/O timing parameters can be easily found in their corresponding datasheets. Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. However, PCB SI degradation is not so straight forward.
In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design guidelines are provided as a reference of an interconnect system that satisfies both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Variation from these recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab measurements
|Configuration||Asymmetric dual stripline|
|Etch thickness||1.0 oz copper (1.2 mil)|
|Flex etch thickness||0.5 oz copper (0.6 mil)|
|Single-ended signal impedance||50 Ω (± 10%)|
|Differential signal impedance||100 Ω differential (± 10%)|
Reference plane 1 is assumed to be a ground plane for proper return path.
Reference plane 2 is assumed to be the I/O power plane or ground
|Dielectric FR4, (Er)||4.2 (nominal)|
|Signal trace distance to reference plane 1 (H1)||5.0 mil (nominal)|
|Signal trace distance to reference plane 2 (H2)||34.2 mil (nominal)|
|PARAMETER||APPLICATION||SINGLE-ENDED SIGNAL||DIFFERENTIAL PAIRS||UNIT|
|Line width (W)(1)||Escape Routing in Ball Field||4 (0.1)||4 (0.1)||mil (mm)|
|PCB Etch Data or Control||7 (0.18)||4.25 (0.11)||mil (mm)|
|PCB Etch Clocks||7 (0.18)||4.25 (0.11)||mil (mm)|
|Minimum Line spacing to other signals (S)||Escape Routing in Ball Field||4 (0.1)||4 (0.1)||mil (mm)|
|PCB Etch Data or Control||10 (0.25)||20 (0.51)||mil (mm)|
|PCB Etch Clocks||20 (0.51)||20 (0.51)||mil (mm)|
|SIGNAL GROUP LENGTH MATCHING|
|I/F||SIGNAL GROUP||REFERENCE SIGNAL||MAX MISMATCH||UNIT|
|DMD (LVDS)||SCA_P,SCA_N, DDA_P(15:0), DDA_N(15:0)||DCKA_P, DCKA_N||±150 (±3.81)||mil (mm)|
|DMD (LVDS)||SCB_P,SCB_N, DDB_P(15:0), DDB_N(15:0)||DCKB_P, DCKB_N||±150 (±3.81)||mil (mm)|
Number of layer changes:
Connector (DMD-LVDS I/F bus only) - High Speed Connectors that meet the following requirements should be used:
|● Differential Crosstalk||<5 %|
|● Differential Impedance||75-125 ohms|
Routing requirements for right angle connectors:
When using right angle connectors, P-N pairs should be routed in same row to minimize delay mismatch.
When using right angle connectors, propagation delay difference for each row should be accounted for on associated PCB etch lengths.