DLPS117B July   2018  – October 2020 DLPC6421

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  System Oscillators Timing Requirements
    7. 6.7  Test and Reset Timing Requirements
    8. 6.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 6.9  Port 1 Input Pixel Timing Requirements
    10. 6.10 DMD LVDS Interface Timing Requirements
    11. 6.11 Synchronous Serial Port (SSP) Interface Timing Requirements
    12. 6.12 Programmable Output Clocks Switching Characteristics
    13. 6.13 Synchronous Serial Port Interface (SSP) Switching Characteristics
    14. 6.14 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1 System Reset Operation
        1. 7.2.1.1 Power-up Reset Operation
        2. 7.2.1.2 System Reset Operation
      2. 7.2.2 Spread Spectrum Clock Generator Support
      3. 7.2.3 GPIO Interface
      4. 7.2.4 Source Input Blanking
      5. 7.2.5 Video Graphics Processing Delay
      6. 7.2.6 Program Memory Flash
      7. 7.2.7 Calibration and Debug Support
      8. 7.2.8 Board Level Test Support
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Recommended MOSC Crystal Oscillator Configuration
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 General Handling Guidelines for Unused CMOS-type Pins
  9. Power Supply Recommendations
    1. 9.1 System Power Regulations
    2. 9.2 System Power-Up Sequence
    3. 9.3 Power-On Sense (POSENSE) Support
    4. 9.4 System Environment and Defaults
      1. 9.4.1 DLPC6421 System Power-Up and Reset Default Conditions
      2. 9.4.2 1.1-V System Power
      3. 9.4.3 1.8-V System Power
      4. 9.4.4 3.3-V System Power
      5. 9.4.5 Power Good (PWRGOOD) Support
      6. 9.4.6 I2C BUSY (I2C_BUSY)
      7. 9.4.7 5V Tolerant Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout Guidelines for Internal DLPC6421 Power
      2. 10.1.2 DMD Interface Considerations
      3. 10.1.3 Layout Example
      4. 10.1.4 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Video Timing Parameter Definitions
      2. 11.1.2 Device Markings
        1. 11.1.2.1 Device Marking Description
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Synchronous Serial Port Interface (SSP) Switching Characteristics

Over operating free-air temperature range, CL(min timing) = 5 pF, CL(max timing) = 50 pF (unless otherwise noted)
PARAMETERTEST CONDITIONSFROM (INPUT)TO (OUTPUT)MINMAXUNIT
fclockClock Frequency, SSPx_CLKN/ASSPx_CLK7325000kHz
tcCycle time, SSPx_CLKN/ASSPx_CLK0.04013.6µs
tW(H)Pulse Duration, high50% to 50% reference points (signal)N/ASSPx_CLK40%
tW(L)Pulse Duration, low50% to 50% reference points (signal)N/ASSPx_CLK40%
SSP Master(1)
tpdOutput Propagation, Clock to Q, SSPx_DO(2)SSPx_CLK↓SSPx_DO-55ns
tpdOutput Propagation, Clock to Q, SSPx_DO(2)SSPx_CLK↑SSPx_DO-55ns
SSP Slave(1)
tpdOutput Propagation, Clock to Q, SSPx_DO(2)SSPx_CLK↓SSPx_DO034ns
tpdOutput Propagation, Clock to Q, SSPx_DO(2)SSPx_CLK↑SSPx_DO034ns
The SSP can be used as an SSP Master, or as an SSP Slave. When used as a Master, the SSP can be configured to sample DI with the same internal clock edge used to transmit the next DO. This essentially provides a full cycle rather than a half cycle timing path, allowing operation at higher SPI clock frequencies.
The SSP can be configured into four different operational modes/configurations.
Table 6-1 SSP Clock Operational Modes
SPI Clocking ModeSPI Clock Polarity (CPOL)SPI Clock Phase (CPHA)
000
101
210
311