DLPS117B July   2018  – October 2020 DLPC6421

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  System Oscillators Timing Requirements
    7. 6.7  Test and Reset Timing Requirements
    8. 6.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 6.9  Port 1 Input Pixel Timing Requirements
    10. 6.10 DMD LVDS Interface Timing Requirements
    11. 6.11 Synchronous Serial Port (SSP) Interface Timing Requirements
    12. 6.12 Programmable Output Clocks Switching Characteristics
    13. 6.13 Synchronous Serial Port Interface (SSP) Switching Characteristics
    14. 6.14 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1 System Reset Operation
        1. 7.2.1.1 Power-up Reset Operation
        2. 7.2.1.2 System Reset Operation
      2. 7.2.2 Spread Spectrum Clock Generator Support
      3. 7.2.3 GPIO Interface
      4. 7.2.4 Source Input Blanking
      5. 7.2.5 Video Graphics Processing Delay
      6. 7.2.6 Program Memory Flash
      7. 7.2.7 Calibration and Debug Support
      8. 7.2.8 Board Level Test Support
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Recommended MOSC Crystal Oscillator Configuration
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 General Handling Guidelines for Unused CMOS-type Pins
  9. Power Supply Recommendations
    1. 9.1 System Power Regulations
    2. 9.2 System Power-Up Sequence
    3. 9.3 Power-On Sense (POSENSE) Support
    4. 9.4 System Environment and Defaults
      1. 9.4.1 DLPC6421 System Power-Up and Reset Default Conditions
      2. 9.4.2 1.1-V System Power
      3. 9.4.3 1.8-V System Power
      4. 9.4.4 3.3-V System Power
      5. 9.4.5 Power Good (PWRGOOD) Support
      6. 9.4.6 I2C BUSY (I2C_BUSY)
      7. 9.4.7 5V Tolerant Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout Guidelines for Internal DLPC6421 Power
      2. 10.1.2 DMD Interface Considerations
      3. 10.1.3 Layout Example
      4. 10.1.4 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Video Timing Parameter Definitions
      2. 11.1.2 Device Markings
        1. 11.1.2.1 Device Marking Description
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

DMD LVDS Interface Timing Requirements

ParameterFROM (INPUT)TO (OUTPUT)MINMAXUNIT
fclockClock frequency, DCK_AN/ADCK_A100400MHz
tCCycle time, DCK_A(1)N/ADCK_A2475.3ps
tW(H)Pulse duration, highN/ADCK_A1093ps
tW(L)Pulse duration, lowN/ADCK_A1093ps
ttTransition time, tt= tf/trN/ADCK_A100400ps
tosuOutput Setup time at max clock rate(4)DCK_A↑↓SCA, DDA(15:0)438ps
tohOutput hold time at max clock rate(4)DCK_A↑↓SCA, DDA(15:0)438ps
fclockClock frequency, DCK_BN/ADCK_B100400MHz
tCCycle time, DCK_B(1)N/ADCK_B2475.3ps
tW(H)Pulse duration, highN/ADCK_B1093ps
tW(L)Pulse duration, lowN/ADCK_B1093ps
ttTransition time, tt= tf/trN/ADCK_B100400ps
tosuOutput Setup time at max clock rate(4)DCK_B↑↓SCA, DDB(15:0)438ps
tohOutput hold time at max clock rate(4)DCK_B↑↓SCA, DDB(15:0)438ps
tskOutput Skew, Channel A to Channel BDCK_A↑DCK_B↑250ps
The minimum cycle time (tc) for DCK_A and DCL_B includes 1.0% spread spectrum modulation. User must verify that DMD can support this rate.
Output Setup & Hold times for DMD clock frequencies below the maximum can be calculated as follows: tosu(fclock) = tosu(fmax) + 250000*(1/fclock – 1/400) & toh(fclock) = toh(fmax) + 250000*(1/fclock – 1/400) where fclock is in MHz.