DLPS117B July   2018  – October 2020 DLPC6421

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  System Oscillators Timing Requirements
    7. 6.7  Test and Reset Timing Requirements
    8. 6.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 6.9  Port 1 Input Pixel Timing Requirements
    10. 6.10 DMD LVDS Interface Timing Requirements
    11. 6.11 Synchronous Serial Port (SSP) Interface Timing Requirements
    12. 6.12 Programmable Output Clocks Switching Characteristics
    13. 6.13 Synchronous Serial Port Interface (SSP) Switching Characteristics
    14. 6.14 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1 System Reset Operation
        1. 7.2.1.1 Power-up Reset Operation
        2. 7.2.1.2 System Reset Operation
      2. 7.2.2 Spread Spectrum Clock Generator Support
      3. 7.2.3 GPIO Interface
      4. 7.2.4 Source Input Blanking
      5. 7.2.5 Video Graphics Processing Delay
      6. 7.2.6 Program Memory Flash
      7. 7.2.7 Calibration and Debug Support
      8. 7.2.8 Board Level Test Support
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Recommended MOSC Crystal Oscillator Configuration
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 General Handling Guidelines for Unused CMOS-type Pins
  9. Power Supply Recommendations
    1. 9.1 System Power Regulations
    2. 9.2 System Power-Up Sequence
    3. 9.3 Power-On Sense (POSENSE) Support
    4. 9.4 System Environment and Defaults
      1. 9.4.1 DLPC6421 System Power-Up and Reset Default Conditions
      2. 9.4.2 1.1-V System Power
      3. 9.4.3 1.8-V System Power
      4. 9.4.4 3.3-V System Power
      5. 9.4.5 Power Good (PWRGOOD) Support
      6. 9.4.6 I2C BUSY (I2C_BUSY)
      7. 9.4.7 5V Tolerant Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout Guidelines for Internal DLPC6421 Power
      2. 10.1.2 DMD Interface Considerations
      3. 10.1.3 Layout Example
      4. 10.1.4 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Video Timing Parameter Definitions
      2. 11.1.2 Device Markings
        1. 11.1.2.1 Device Marking Description
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

GUID-46A519D1-E470-49C8-A3F5-BC2E492F7567-low.jpgFigure 5-1 ZPC Package516-Pin BGABottom View
Table 5-1 Pin Configurations and Functions
PIN (1) I/O (2) DESCRIPTION
NAME NO.
POSENSE P22 I4 Power-On Sense, High true, signal provided from an external voltage monitor circuit. This signal should be driven active (high) when all DLPC6421 supply voltages have reached 90% of their specified minimum voltage. This signal should be driven inactive (low) after the falling edge of PWRGOOD as specified.
PWRGOOD T26 I4 Power Good, High true, signal from external power supply or voltage monitor. A high value indicates all power is within operating voltage specs and the system is safe to exit its reset state. A transition from high to low is used to indicate that the controller or DMD supply voltage will drop below their rated minimum level. This transition must occur prior to the supply voltage drop as specified. During this interval, POSENSE must remain active high. This is an early warning of an imminent power loss condition. This warning is required to enhance long term DMD reliability. A DMD park followed by a full controller reset is performed by the DLPC6421 controller when PWRGOOD goes low for the specified minimum, protecting the DMD. This minimum de-assertion time is used to protect the input from glitches. Following this the DLPC6421 controller will be held in its reset state as long as PWRGOOD is low. PWRGOOD must be driven high for normal operation. The DLPC6421 controller will acknowledge PWRGOOD as active once it’s been driven high for it’s specified minimum time. Uses hysteresis.
EXT_ARTZ T24 O2 General purpose, LOW true, reset output. This output is asserted low immediately upon asserting power-up reset (POSENSE) low and remains low while POSENSE remains low. EXT_ARSTZ continues to be held low after the release of power-up reset (that is, POSENSE set high) until released by software. EXT_ARSTZ is also asserted low approximately 5 µs after the detection of a PWRGOOD or any internally generated reset. In all cases it will remain active for a minimum of 2 ms. Note that the DLPC6421 contains a software register that can be used to independently drive this output.
MTR_ARTZ T25 O2 Reserved
BOARD LEVEL TEST AND INITIALIZATION (3)
TDI N25 I4 JTAG serial data in
TCK N24 I4 JTAG serial data clock
TMS1 P25 I4 JTAG test mode select
TMS2 P26 I4 JTAG test mode select
TDO1 N23 O5 JTAG serial data out
TDO2 N22 O5 JTAG serial data out
TRSTZ M23 I4 JTAG reset. This signal includes an internal pull-up and utilizes hysteresis. This pin should be pulled high (or left unconnected) when the JTAG interface is in use for boundary scan or ARM debug. Connect this pin to ground otherwise. Failure to tie this pin low during normal operation will cause startup and initialization problems.
RTCK E4 O2 JTAG return clock
ETM_PIPESTAT_2 A4 B2 ETM trace port pipeline status. Indicates the pipeline status of the ARM core. These signals include internal pull-downs.
ETM_PIPESTAT_1 B5 B2
ETM_PIPESTAT_0 C6 B2
ETM_TRACESYNC A5 B2 ETM trace port synchronization signal, indicating the start of a branch sequence on the trace packet port. This signal includes an internal pull-down.
ETM_TRACECLK D7 B2 ETM trace port clock. This signal includes an internal pull-down.
ICTSEN M24 I4 IC tri-State enable (active high). Asserting high will tri-state all outputs except the JTAG interface. This signal includes an internal pull-down however TI recommends an external pull-down for added protection. Uses hysteresis.
TSTPT_7 E8 B2 Test pin 7 - This signal provides internal pull-downs.
Normal use: reserved for test output. Should be left open or unconnected for normal use.
TSTPT_6 B4 B2 Test pin 6 - This signal provides internal pull-downs.
Normal use: reserved for test output. Should be left open or unconnected for normal use.
TSTPT_5 C4 B2 Test pin 5 - This signal provides internal pull-downs.
Normal use: reserved for test output. Should be left open or unconnected for normal use.
TSTPT_4 E7 B2 Test pin 4 - This signal provides internal pull-downs.
Normal use: reserved for test output. Should be left open or unconnected for normal use.
TSTPT_3 D5 B2 Test pin 3 - This signal provides internal pull-downs.
Normal use: reserved for test output. Should be left open or unconnected for normal use.
TSTPT_2 E6 B2 Test pin 2 - This signal provides internal pull-downs. Additionally, TI recommends that jumper options be provided for connecting TSTPT(2:0) to external pull-ups.
TSTPT_1 D3 B2 Test pin 1 - This signal provides internal pull-downs. Additionally, TI recommends that jumper options be provided for connecting TSTPT(2:0) to external pull-ups.
TSTPT_0 C2 B2 Test pin 0 - This signal provides internal pull-downs. Additionally, TI recommends that jumper options be provided for connecting TSTPT(2:0) to external pull-ups.
DEVICE TEST
HW_TEST_EN M25 I4 Device manufacturing test enable; This signal includes an internal pull-down and utilizes hysteresis. TI recommends that this signal be tied to an external ground in normal operation for added protection.
ANALOG FRONT END
AFE_ARSTZ AC12 O2 Reserved
AFE_CLK AD12 O6 Reserved
AFE_IRQ AB13 I4 Reserved
PORT1 and PORT 2 CHANNEL DATA and CONTROL(4)(5)(6)(7)
P_CLK1 AE22 I4 Input port data pixel write clock (selectable as rising or falling edge triggered, and which port it is associated with (A or B or (A and B))). This signal includes an internal pull-down.
P_CLK2 W25 I4 Input port data pixel write clock (selectable as rising or falling edge triggered, and which port it is associated with (A or B or (A and B))). This signal includes an internal pull-down.
P_CLK3 AF23 I4 Input port data pixel write clock (selectable as rising or falling edge triggered, and which port it is associated with (A or B or (A and B))). This signal includes an internal pull-down.
P_DATAEN1 AF22 I4 Active high data enable. Selectable as to which port it is associated with (A or B or (A and B)).This signal includes an internal pull-down.
P_DATAEN2 W24 I4 Active high data enable. Selectable as to which port it is associated with (A or B or (A and B)).This signal includes an internal pull-down.
P1_A_9 AD15 I4 Port 1 A Channel Input Pixel Data (bit weight 128)
P1_A_8 AE15 I4 Port 1 A Channel Input Pixel Data (bit weight 64)
P1_A_7 AE14 I4 Port 1 A Channel Input Pixel Data (bit weight 32)
P1_A_6 AE13 I4 Port 1 A Channel Input Pixel Data (bit weight 16)
P1_A_5 AD13 I4 Port 1 A Channel Input Pixel Data (bit weight 8)
P1_A_4 AC13 I4 Port 1 A Channel Input Pixel Data (bit weight 4)
P1_A_3 AF14 I4 Port 1 A Channel Input Pixel Data (bit weight 2)
P1_A_2 AF13 I4 Port 1 A Channel Input Pixel Data (bit weight 1)
P1_A_1 AF12 I4 Port 1 A Channel Input Pixel Data (bit weight 0.5)
P1_A_0 AE12 I4 Port 1 A Channel Input Pixel Data (bit weight 0.25)
P1_B_9 AF18 I4 Port 1 B Channel Input Pixel Data (bit weight 128)
P1_B_8 AB18 I4 Port 1 B Channel Input Pixel Data (bit weight 64)
P1_B_7 AC15 I4 Port 1 B Channel Input Pixel Data (bit weight 32)
P1_B_6 AC16 I4 Port 1 B Channel Input Pixel Data (bit weight 16)
P1_B_5 AD16 I4 Port 1 B Channel Input Pixel Data (bit weight 8)
P1_B_4 AE16 I4 Port 1 B Channel Input Pixel Data (bit weight 4)
P1_B_3 AF16 I4 Port 1 B Channel Input Pixel Data (bit weight 2)
P1_B_2 AF15 I4 Port 1 B Channel Input Pixel Data (bit weight 1)
P1_B_1 AC14 I4 Port 1 B Channel Input Pixel Data (bit weight 0.5)
P1_B_0 AD14 I4 Port 1 B Channel Input Pixel Data (bit weight 0.25)
P1_C_9 AD20 I4 Port 1 C Channel Input Pixel Data (bit weight 128)
P1_C_8 AE20 I4 Port 1 C Channel Input Pixel Data (bit weight 64)
P1_C_7 AE21 I4 Port 1 C Channel Input Pixel Data (bit weight 32)
P1_C_6 AF21 I4 Port 1 C Channel Input Pixel Data (bit weight 16)
P1_C_5 AD19 I4 Port 1 C Channel Input Pixel Data (bit weight 8)
P1_C_4 AE19 I4 Port 1 C Channel Input Pixel Data (bit weight 4)
P1_C_3 AF19 I4 Port 1 C Channel Input Pixel Data (bit weight 2)
P1_C_2 AF20 I4 Port 1 C Channel Input Pixel Data (bit weight 1)
P1_C_1 AC19 I4 Port 1 C Channel Input Pixel Data (bit weight 0.5)
P1_C_0 AE18 I4 Port 1 C Channel Input Pixel Data (bit weight 0.25)
P1_VSYNC AC20 B2 Port 1 Vertical Sync. This signal includes an internal pull-down. While intended to be associated with Port 1, it can be programmed for use with Port 2.
P1_HSYNC AD21 B2 Port 1 Horizontal Sync. This signal includes an internal pull-down. While intended to be associated with Port 1, it can be programmed for use with Port 2.
P2_A_9 AD26 I4 Port 2 A Channel Input Pixel Data (bit weight 128)
P2_A_8 AD25 I4 Port 2 A Channel Input Pixel Data (bit weight 64)
P2_A_7 AB21 I4 Port 2 A Channel Input Pixel Data (bit weight 32)
P2_A_6 AC22 I4 Port 2 A Channel Input Pixel Data (bit weight 16)
P2_A_5 AD23 I4 Port 1 A Channel Input Pixel Data (bit weight 8)
P2_A_4 AB20 I4 Port 2 A Channel Input Pixel Data (bit weight 4)
P2_A_3 AC21 I4 Port 2 A Channel Input Pixel Data (bit weight 2)
P2_A_2 AD22 I4 Port 2 A Channel Input Pixel Data (bit weight 1)
P2_A_1 AE23 I4 Port 2 A Channel Input Pixel Data (bit weight 0.5)
P2_A_0 AB19 I4 Port 2 A Channel Input Pixel Data (bit weight 0.25)
P2_B_9 Y22 I4 Port 2 B Channel Input Pixel Data (bit weight 128)
P2_B_8 AB26 I4 Port 2 B Channel Input Pixel Data (bit weight 64)
P2_B_7 AA23 I4 Port 2 B Channel Input Pixel Data (bit weight 32)
P2_B_6 AB25 I4 Port 2 B Channel Input Pixel Data (bit weight 16)
P2_B_5 AA22 I4 Port 2 B Channel Input Pixel Data (bit weight 8)
P2_B_4 AB24 I4 Port 2 B Channel Input Pixel Data (bit weight 4)
P2_B_3 AC26 I4 Port 2 B Channel Input Pixel Data (bit weight 2)
P2_B_2 AB23 I4 Port 2 B Channel Input Pixel Data (bit weight 1)
P2_B_1 AC25 I4 Port 2 B Channel Input Pixel Data (bit weight 0.5)
P2_B_0 AC24 I4 Port 2 B Channel Input Pixel Data (bit weight 0.25)
P2_C_9 W23 I4 Port 2 C Channel Input Pixel Data (bit weight 128)
P2_C_8 V22 I4 Port 2 B Channel Input Pixel Data (bit weight 64)
P2_C_7 Y26 I4 Port 2 C Channel Input Pixel Data (bit weight 32)
P2_C_6 Y25 I4 Port 2 B Channel Input Pixel Data (bit weight 16)
P2_C_5 Y24 I4 Port 2 C Channel Input Pixel Data (bit weight 8)
P2_C_4 Y23 I4 Port 2 B Channel Input Pixel Data (bit weight 4)
P2_C_3 W22 I4 Port 2 C Channel Input Pixel Data (bit weight 2)
P2_C_2 AA26 I4 Port 2 B Channel Input Pixel Data (bit weight 1)
P2_C_1 AA25 I4 Port 2 C Channel Input Pixel Data (bit weight 0.5)
P2_C_0 AA24 I4 Port 2 B Channel Input Pixel Data (bit weight 0.25)
P2_VSYNC U22 B2 Port 2 Vertical Sync. This signal includes an internal pull-down. While intended to be associated with Port 2, it can be programmed for use with Port1.
P2_HSYNC W26 B2 Port 2 Horizontal Sync. This signal includes an internal pull-down. While intended to be associated with Port 2, it can be programmed for use with Port1.
ALF INPUT PORT CONTROL
ALF_VSYNC AF11 I4 Reserved
ALF_HSYNC AD11 I4 Reserved
ALF_CSYNC AE11 I4 Reserved
DMD RESET and BIAS CONTROL
DADOEZ AE7 O5 Reserved
DADADDR_3 AD6 O5 Reserved
DADADDR_2 AE5 O5
DADADDR_1 AF4 O5
DADADDR_0 AB8 O5
DADMODE_1 AD7 O5 Reserved
DADMODE_0 AE6 O5
DADSEL_1 AE4 O5 Reserved
DADSEL_0 AC7 O5
DADSTRB AF5 O5 Reserved
DAD_INTZ AC8 I4 Reserved
DMD LVDS INTERFACE
DCKA_P V4 O7 DMD, LVDS I/F channel A, differential clock
DCKA_N V3 O7
SCA_P V2 O7 DMD, LVDS I/F channel A, differential serial control
SCA_N V1 O7
DDA_P_15 P4 O7 DMD, LVDS I/F channel A, differential serial data
DDA_N_15 P3 O7 DMD, LVDS I/F channel A, differential serial data
DDA_P_14 P2 O7 DMD, LVDS I/F channel A, differential serial data
DDA_N_14 P1 O7 DMD, LVDS I/F channel A, differential serial data
DDA_P_13 R4 O7 DMD, LVDS I/F channel A, differential serial data
DDA_N_13 R3 O7 DMD, LVDS I/F channel A, differential serial data
DDA_P_12 R2 O7 DMD, LVDS I/F channel A, differential serial data
DDA_N_12 R1 O7 DMD, LVDS I/F channel A, differential serial data
DDA_P_11 T4 O7 DMD, LVDS I/F channel A, differential serial data
DDA_N_11 T3 O7 DMD, LVDS I/F channel A, differential serial data
DDA_P_10 T2 O7 DMD, LVDS I/F channel A, differential serial data
DDA_N_10 T1 O7 DMD, LVDS I/F channel A, differential serial data
DDA_P_9 U4 O7 DMD, LVDS I/F channel A, differential serial data
DDA_N_9 U3 O7 DMD, LVDS I/F channel A, differential serial data
DDA_P_8 U2 O7 DMD, LVDS I/F channel A, differential serial data
DDA_N_8 U1 O7 DMD, LVDS I/F channel A, differential serial data
DDA_P_7 W4 O7 DMD, LVDS I/F channel A, differential serial data
DDA_N_7 W3 O7 DMD, LVDS I/F channel A, differential serial data
DDA_P_6 W2 O7 DMD, LVDS I/F channel A, differential serial data
DDA_N_6 W1 O7 DMD, LVDS I/F channel A, differential serial data
DDA_P_5 Y2 O7 DMD, LVDS I/F channel A, differential serial data
DDA_N_5 Y1 O7 DMD, LVDS I/F channel A, differential serial data
DDA_P_4 Y4 O7 DMD, LVDS I/F channel A, differential serial data
DDA_N_4 Y3 O7 DMD, LVDS I/F channel A, differential serial data
DDA_P_3 AA2 O7 DMD, LVDS I/F channel A, differential serial data
DDA_N_3 AA1 O7 DMD, LVDS I/F channel A, differential serial data
DDA_P_2 AA4 O7 DMD, LVDS I/F channel A, differential serial data
DDA_N_2 AA3 O7 DMD, LVDS I/F channel A, differential serial data
DDA_P_1 AB2 O7 DMD, LVDS I/F channel A, differential serial data
DDA_N_1 AB1 O7 DMD, LVDS I/F channel A, differential serial data
DDA_P_0 AC2 O7 DMD, LVDS I/F channel A, differential serial data
DDA_N_0 AC1 O7 DMD, LVDS I/F channel A, differential serial data
DCKB_P J3 O7 DMD, LVDS I/F channel A, differential clock
DCKB_N J4 O7 DMD, LVDS I/F channel A, differential clock
SCB_P J1 O7 DMD, LVDS I/F channel A, differential serial control
SCB_N J2 O7 DMD, LVDS I/F channel A, differential serial control
DDB_P_15 N1 O7 DMD, LVDS I/F channel B, differential serial data
DDB_N_15 N2 O7 DMD, LVDS I/F channel B, differential serial data
DDB_P_14 N3 O7 DMD, LVDS I/F channel B, differential serial data
DDB_N_14 N4 O7 DMD, LVDS I/F channel B, differential serial data
DDB_P_13 M2 O7 DMD, LVDS I/F channel B, differential serial data
DDB_N_13 M1 O7 DMD, LVDS I/F channel B, differential serial data
DDB_P_12 M3 O7 DMD, LVDS I/F channel B, differential serial data
DDB_N_12 M4 O7 DMD, LVDS I/F channel B, differential serial data
DDB_P_11 L1 O7 DMD, LVDS I/F channel B, differential serial data
DDB_N_11 L2 O7 DMD, LVDS I/F channel B, differential serial data
DDB_P_10 L3 O7 DMD, LVDS I/F channel B, differential serial data
DDB_N_10 L4 O7 DMD, LVDS I/F channel B, differential serial data
DDB_P_9 K1 O7 DMD, LVDS I/F channel B, differential serial data
DDB_N_9 K2 O7 DMD, LVDS I/F channel B, differential serial data
DDB_P_8 K3 O7 DMD, LVDS I/F channel B, differential serial data
DDB_N_8 K4 O7 DMD, LVDS I/F channel B, differential serial data
DDB_P_7 H1 O7 DMD, LVDS I/F channel B, differential serial data
DDB_N_7 H2 O7 DMD, LVDS I/F channel B, differential serial data
DDB_P_6 H3 O7 DMD, LVDS I/F channel B, differential serial data
DDB_N_6 H4 O7 DMD, LVDS I/F channel B, differential serial data
DDB_P_5 G1 O7 DMD, LVDS I/F channel B, differential serial data
DDB_N_5 G2 O7 DMD, LVDS I/F channel B, differential serial data
DDB_P_4 G3 O7 DMD, LVDS I/F channel B, differential serial data
DDB_N_4 G4 O7 DMD, LVDS I/F channel B, differential serial data
DDB_P_3 F1 O7 DMD, LVDS I/F channel B, differential serial data
DDB_N_3 F2 O7 DMD, LVDS I/F channel B, differential serial data
DDB_P_2 F3 O7 DMD, LVDS I/F channel B, differential serial data
DDB_N_2 F4 O7 DMD, LVDS I/F channel B, differential serial data
DDB_P_1 E1 O7 DMD, LVDS I/F channel B, differential serial data
DDB_N_1 E2 O7 DMD, LVDS I/F channel B, differential serial data
DDB_P_0 D1 O7 DMD, LVDS I/F channel B, differential serial data
DDB_N_0 D2 O7 DMD, LVDS I/F channel B, differential serial data
PROGRAM MEMORY (Flash) INTERFACE
PM_CSZ_0 D13 O5 N/A
PM_CSZ_1 E12 O5 Boot Flash Chip Select (active low)
PM_CSZ_2 A13 O5 N/A
PM_ADDR_20 D12 O5 Address Bit 20
PM_ADDR_19 C12 O5 Address Bit 19
PM_ADDR_18 B11 O5 Address Bit 18
PM_ADDR_17 A11 O5 Address Bit 17
PM_ADDR_16 D11 O5 Address Bit 16
PM_ADDR_15 C11 O5 Address Bit 15
PM_ADDR_14 E10 O5 Address Bit 14
PM_ADDR_13 D10 O5 Address Bit 13
PM_ADDR_12 C10 O5 Address Bit 12
PM_ADDR_11 B9 O5 Address Bit 11
PM_ADDR_10 A9 O5 Address Bit 10
PM_ADDR_9 E9 O5 Address Bit 9
PM_ADDR_8 D9 O5 Address Bit 8
PM_ADDR_7 C9 O5 Address Bit 7
PM_ADDR_6 B8 O5 Address Bit 6
PM_ADDR_5 A8 O5 Address Bit 5
PM_ADDR_4 D8 O5 Address Bit 4
PM_ADDR_3 C8 O5 Address Bit 3
PM_ADDR_2 B7 O5 Address Bit 2
PM_ADDR_1 A7 O5 Address Bit 1
PM_ADDR_0 C7 O5 Address Bit 0 (LSB)
PM_WEZ B12 O5 Write Enable (active low)
PM_OEZ C13 O5 Output Enable (active low)
PM_BLSZ_1 B6 O5 N/A
PM_BLSZ_0 A6 O5 N/A
PM_DATA_15 C17 B5 Data Bit (15)
PM_DATA_14 B16 B5 Data Bit (14)
PM_DATA_13 A16 B5 Data Bit (13)
PM_DATA_12 A15 B5 Data Bit (12)
PM_DATA_11 B15 B5 Data Bit (11)
PM_DATA_10 D16 B5 Data Bit (10)
PM_DATA_9 C16 B5 Data Bit (9)
PM_DATA_8 E14 B5 Data Bit (8)
PM_DATA_7 D15 B5 Data Bit (7)
PM_DATA_6 C15 B5 Data Bit (6)
PM_DATA_5 B14 B5 Data Bit (5)
PM_DATA_4 A14 B5 Data Bit (4)
PM_DATA_3 E13 B5 Data Bit (3)
PM_DATA_2 D14 B5 Data Bit (2)
PM_DATA_1 C14 B5 Data Bit (1)
PM_DATA_0 B13 B5 Data Bit (0)
PERIPHERAL INTERFACE
IIC0_SCL A10 B8 I2C Bus 0, Clock. This bus support 400 kHz, fast mode operation. This signal requires an external pull-up to 3.3-V. The minimum acceptable pull-up value is 1 kΩ. This input is not 5 V tolerant.
IIC0_SDA B10 B8 2C Bus 0, Data. This bus support 400 kHz, fast mode operation. This signal requires an external pull-up to 3.3-V. The minimum acceptable pull-up value is 1 kΩ. This input is not 5 V tolerant.
SSP0_CLK AD4 B5 Synchronous Serial Port 0, clock
SSP0_RXD AD5 I4 Synchronous Serial Port 0, receive data in
SSP0_TXD AB7 O5 Synchronous Serial Port 0, transmit data out
SSP0_CSZ_0 AC5 B5 Synchronous Serial Port 0, chip select 0 (active low)
SSP0_CSZ_1 AB6 B5 Synchronous Serial Port 0, chip select 1 (active low)
SSP0_CSZ_2 AC3 B5 Synchronous Serial Port 0, chip select 2 (active low)
UART0_TXD AB3 O5 UART0 transmit data output
UART0_RXD AD1 O5 UART0 receive data input
UART0_RTSZ AD2 O5 UART0 ready to send hardware flow control output (active low)
UART0_CTSZ AE2 I4 UART0 clear to send hardware flow control input (active low)
USB_DAT_N C5 B9 USB D- I/O
USB_DAT_P D6 B9 USB D+ I/O
PMD_INTZ AE8 I4 This signal requires an external pull-up. Uses hysteresis.
CW_PWM AD8 O5 Reserved
CW_INDEX AF7 O5 Reserved
LMPCTRL AC9 O5 Reserved
LMPSTAT AF8 I4 Reserved
GENERAL PURPOSE I/O (GPIO)(8) Software Function 1 Alternate Software Function 2
GPIO_82 E3 B5 N/A N/A
GPIO_81 AB10 B2 N/A N/A
GPIO_80 AD9 B2 N/A N/A
GPIO_79 AE9 B2 HEARTBEAT(O) N/A
GPIO_78 AF9 B2 FIELD_3D_LR (I) N/A
GPIO_77 AB11 B2 SAS_INTGTR_EN (O) N/A
GPIO_76 AC10 B2 SAS_CSZ (O) N/A
GPIO_75 AD10 B2 SAS_DO (O) SENSE_FREQ_IN (I)
GPIO_74 AE10 B2 SAS_DI (I) N/A
GPIO_73 AF10 B2 SAS_CLK (O) N/A
GPIO_72 K24 B2 SSP2_DI (I) N/A
GPIO_71 K23 B2 SSP2_CLK (B) N/A
GPIO_70 K22 B2 SSP2_CSZ_1 (B) N/A
GPIO_69 J26 B2 SSP2_CSZ_0 (B) N/A
GPIO_68 J25 B2 SSP2_DO (O) N/A
GPIO_67 J24 B2 N/A N/A
GPIO_66 J23 B2 N/A N/A
GPIO_65 J22 B2 N/A N/A
GPIO_64 H26 B2 N/A N/A
GPIO_63 H25 B2 N/A N/A
GPIO_62 H24 B2 N/A N/A
GPIO_61 H23 B2 N/A N/A
GPIO_60 H22 B2 N/A N/A
GPIO_59 G26 B2 N/A N/A
GPIO_58 G25 B2 LED_SENSE_PULSE (O) N/A
GPIO_57 F25 B2 N/A N/A
GPIO_56 G24 B2 I2C_BUSY (O) SYSTEM_BUSY (O)
GPIO_55 G23 B2 N/A N/A
GPIO_54 F26 B2 N/A N/A
GPIO_53 E26 B2 N/A N/A
GPIO_52 AB12 B2 N/A N/A
GPIO_51 AC11 B2 N/A N/A
GPIO_50 V23 B2 N/A HBT_CLKOUT (O)
GPIO_49 V24 B2 N/A HBT_DO (O)
GPIO_48 V25 B2 N/A N/A
GPIO_47 V26 B2 N/A N/A
GPIO_46 T22 B2 PROJ_ON (I) N/A
GPIO_45 U23 B2 N/A N/A
GPIO_44 U24 B2 N/A HBT_CLKIN_0 (I)
GPIO_43 U25 B2 N/A HBT_DI_0 (I)
GPIO_42 U26 B2 N/A SSP0_CSZ4 (B)
GPIO_41 R22 B2 N/A DASYNC (I)
GPIO_40 T23 B2 N/A N/A
GPIO_39 F24 B2 SW reserved (Boot Hold) SW reserved (Boot Hold)
GPIO_38 E25 B2 SW reserved (USB Enumeration Enable) SW reserved (USB Enumeration Enable)
GPIO_37 G22 B2 N/A N/A
GPIO_36 A12 B2 PM_ADDR_22 (O) N/A
GPIO_35 E11 B2 PM_ADDR_21 (O) N/A
GPIO_34 F23 B2 SSP1_CSZ_1 (B) N/A
GPIO_33 D26 B2 SSP1_CSZ_0 (B) N/A
GPIO_32 E24 B2 SSP1_DO (O) N/A
GPIO_31 F22 B2 SSP1_DI (I) N/A
GPIO_30 D25 B2 SSP1_CLK (B) N/A
GPIO_29 E23 B2 N/A N/A
GPIO_28 C26 B2 N/A N/A
GPIO_27 AB4 B2 SSP0_CSZ3 (B) N/A
GPIO_26 D24 B2 Blue LED enable (O) N/A
GPIO_25 C25 B2 Green LED enable (O) N/A
GPIO_24 B26 B2 Red LED enable (O) N/A
GPIO_23 E21 B2 N/A N/A
GPIO_22 D22 B2 N/A N/A
GPIO_21 E20 B2 N/A N/A
GPIO_20 C23 B2 N/A N/A
GPIO_19 D21 B2 N/A N/A
GPIO_18 B24 B2 N/A N/A
GPIO_17 C22 B2 N/A N/A
GPIO_16 B23 B2 N/A N/A
GPIO_15 E19 B2 I2C_1 SDA (B) N/A
GPIO_14 D20 B2 I2C_1 SCL (B) N/A
GPIO_13 C21 B2 N/A I2C_2 SDA (B)
GPIO_12 B22 B2 N/A I2C_2 SCL (B)
GPIO_11 A23 B2 N/A N/A
GPIO_10 A22 B2 N/A N/A
GPIO_9 B21 B2 N/A N/A
GPIO_8 A21 B2 N/A N/A
GPIO_7 A20 B2 N/A N/A
GPIO_6 C20 B2 N/A N/A
GPIO_5 B20 B2 N/A N/A
GPIO_4 B19 B2 N/A N/A
GPIO_3 A19 B2 N/A N/A
GPIO_2 E18 B2 N/A N/A
GPIO_1 D19 B2 N/A N/A
GPIO_0 C19 B2 N/A N/A
CLOCK and PLL SUPPORT
MOSC M26 I10 System clock oscillator input (3.3-V LVTTL). Note that MOSC must be stable a maximum of 25ms after POSENSE transitions from low to high.
MOSCN N26 O10 MOSC crystal return
OCLKA AF6 O5 General purpose output clock A.
DUAL CONTROLLER SUPPORT
SEQ_SYNC AB9 B3 Sequence Sync. This signal is used in multi controller configurations only, in which case the SEQSYNC signal from each controller should be connected together with an external pull-up. This signal should either be pulled high or pulled low and not allowed to float for single controller configurations.
POWER and GROUND
VDD33 F20, F17, F11, F8, L21, R21, Y21, AA19, AA16, AA10, AA7 POWER 3.3-V I/O Power
VDD18 C1, F5, G6, K6, M5, P5, T5, W6, AA5, AE1, H5, N6, T6, AA13, U21, P21, H21, F14 POWER 1.8-V Internal DRAM & LVDS I/O Power
VDD11 F19, F16, F13, F10, F7, H6, L6, P6, U6, Y6, AA8, AA11, AA14, AA17, AA20, W21, T21, N21, K21, G21, L11, T11, T16, L16 POWER 1.1-V Core Power
VDD_PLLD L22 POWER 1.1-V DMD clock generator PLL digital power
VSS_PLLD L23 GROUND 1.1-V DMD clock generator PLL digital ground
VAD_PLLD K25 POWER 1.8-V DMD clock generator PLL analog power
VAS_PLLD K26 GROUND 1.8-V DMD clock generator PLL analog ground
VDD_PLLM1 L26 POWER 1.1-V Master-LS clock generator PLL digital power
VSS_PLLM1 M22 GROUND 1.1-V Master-LS clock generator PLL digital ground
VAD_PLLM1 L24 POWER 1.8-V Master-LS clock generator PLL analog power
VAS_PLLM1 L25 GROUND 1.8-V Master-LS clock generator PLL analog ground
VDD_PLLM2 P23 POWER 1.1-V Master-HS clock generator PLL digital power
VSS_PLLM2 P24 GROUND 1.1-V Master-HS clock generator PLL digital ground
VAD_PLLM2 R25 POWER 1.8-V Master-HS clock generator PLL analog power
VAS_PLLM2 R26 GROUND 1.8-V Master-HS clock generator PLL analog ground
VAD_PLLS R23 POWER 1.1-V video-2X clock generator PLL analog power
VAS_PLLS R24 GROUND 1.1-V video-2X clock generator PLL analog ground
L-VDQPAD_[7:0],
R-VDQPAD_[7:0]
B18, D18, B17, E17, A18, C18, A17, D17, AE17, AC17, AF17, AC18, AB16, AD17, AB17, AD18 RESERVED These should be tied directly to ground for normal operation.
CFO_VDD33 AE26 RESERVED This should be tied directly to 3.3 I/O power (VDD33) for normal operation.
VTEST1, VTEST2, VTEST3, VTEST4 AB14, AB15, E15, E16 RESERVED These should be tied directly to ground for normal operation.
LVDS_AVS1, LVDS_AVS2 V5, K5 POWER These should be tied directly to ground for normal operation.
VPGM AC6 POWER This should be tied directly to ground for normal operation.
GROUND A26, A25, A24, B25, C24, D23, E22, F21, F18, F15, F12, F9, F6, E5, D4, C3, B3, A3, B2, A2, B1, A1 G5, J5, J6, L5, M6, N5, R5, R6, U5, V6, W5, Y5, AA6, AB5, AC4, AD3, AE3, AF3, AF2, AF1, AA9, AA12, AA15, AA18, AA21, AB22, AC23, AD24, AE24, AF24, AE25, AF25, AF26, V21, M21, J21, L15, L14, L13, L12, M16, M15, M14, M13, M12, M11, N16, N15, N14, N13, N12, N11, P16, P15, P14, P13, P12, P11, R16, R15, R14, R13, R12, R11, T15, T14, T13, T12 GROUND Common ground
For instructions on handling unused pins, see Section 8.2.3.
I/O Type: I = Input, O = Output, B = Bidirectional, and H = Hysteresis. See Table 5-2 for subscript explanation.
All JTAG signals are LVTTL compatible.
Ports 1 and 2 can each be used to support multiple source options for a given product. To do so, the data bus from both source components must be connected to the same port pins (1 or 2) and control given to the DLPC6421 device to tri-state the "inactive" source. Tying them together like this will cause some signal degradation due to reflections on the tri-stated path. Given the clock is the most critical signal, Port clocks (1 and 2) are provided to provide an option to improve the signal integrity.
Ports 1 and 2 can be combined into one 60-bit port (typically for high data rate sources) for transmission of two pixels per clock.
The A, B, C input data channels of Ports 1 and 2 can be internally re-configured/ re-mapped for optimum board layout.
Sources feeding less than the full 10-bits per color component channel should be MSB justified when connected to the DLPC6421 controller and the LSBs tied off to zero. For example an 8-bit per color input should be connected to bits 9:2 of the corresponding A, B, C input channel.
GPIO signals must be configured by software for input, output, bidirectional, or open-drain. Some GPIOs have one or more alternate use modes, which are also software configurable. The reset default for all optional GPIOs is as an input signal. However, any alternate function connected to these GPIO pins with the exception of general-purpose clocks and PWM generation, are reset. An external pullup to the 3.3-V supply is required for each signal configured as open-drain. External pullup or pulldown resistors may be required to ensure stable operation before software is able to configure these ports.
Table 5-2 I/O Type Subscript Definition
SUBSCRIPT DESCRIPTION ESD STRUCTURE
2 3.3 LVTTL I/O Buffer with 8 mA drive ESD diode to VDD33 and GROUND
3 3.3 LVTTL I/O Buffer, with 12 mA drive
4 3.3 LVTTL Receiver
5 3.3 LVTTL I/O Buffer with 8 mA drive, with Slew Rate Control
6 3.3 LVTTL I/O Buffer, with programmable 4 mA, 8 mA, or 12 mA drive
7 1.8 LVDS (DMD I/F)
8 3.3 V I2C with 3 mA sink
9 USB Compatible (3.3 V)
10 OSC 3.3 V I/O Compatible LVTTL