DLPS117B July 2018 – October 2020 DLPC6421
Following system power-up, the DLPC6421 device performs a power-up initialization routine that defaults the device to it’s normal power mode, in which ARM9-related clocks are enabled at their full rate and associated resets are released. Most other clocks default to disabled state with associated resets asserted until released by the processor. In addition, the default for system power gating enables all power. These same defaults are also applied as part of all system reset events (Watch Dog timer timeout, reset, etc) that occur without removing or cycling power, with the possible exception of power for the LVDS I/O and internal DRAM.
Following power-up or system reset initialization, the ARM9 boots from an external flash memory after which it enables the rest of the DLPC6421 clocks, and initializes the internal DRAM.