DLPS117B July   2018  – October 2020 DLPC6421

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  System Oscillators Timing Requirements
    7. 6.7  Test and Reset Timing Requirements
    8. 6.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 6.9  Port 1 Input Pixel Timing Requirements
    10. 6.10 DMD LVDS Interface Timing Requirements
    11. 6.11 Synchronous Serial Port (SSP) Interface Timing Requirements
    12. 6.12 Programmable Output Clocks Switching Characteristics
    13. 6.13 Synchronous Serial Port Interface (SSP) Switching Characteristics
    14. 6.14 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1 System Reset Operation
        1. 7.2.1.1 Power-up Reset Operation
        2. 7.2.1.2 System Reset Operation
      2. 7.2.2 Spread Spectrum Clock Generator Support
      3. 7.2.3 GPIO Interface
      4. 7.2.4 Source Input Blanking
      5. 7.2.5 Video Graphics Processing Delay
      6. 7.2.6 Program Memory Flash
      7. 7.2.7 Calibration and Debug Support
      8. 7.2.8 Board Level Test Support
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Recommended MOSC Crystal Oscillator Configuration
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 General Handling Guidelines for Unused CMOS-type Pins
  9. Power Supply Recommendations
    1. 9.1 System Power Regulations
    2. 9.2 System Power-Up Sequence
    3. 9.3 Power-On Sense (POSENSE) Support
    4. 9.4 System Environment and Defaults
      1. 9.4.1 DLPC6421 System Power-Up and Reset Default Conditions
      2. 9.4.2 1.1-V System Power
      3. 9.4.3 1.8-V System Power
      4. 9.4.4 3.3-V System Power
      5. 9.4.5 Power Good (PWRGOOD) Support
      6. 9.4.6 I2C BUSY (I2C_BUSY)
      7. 9.4.7 5V Tolerant Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout Guidelines for Internal DLPC6421 Power
      2. 10.1.2 DMD Interface Considerations
      3. 10.1.3 Layout Example
      4. 10.1.4 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Video Timing Parameter Definitions
      2. 11.1.2 Device Markings
        1. 11.1.2.1 Device Marking Description
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

Over recommended operating conditions(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage USB (9) 2.0 V
OSC (10) 2.0
3.3-V LVTTL (1,2,3,4) 2.0
3.3-V I2C (8) 2.4 VDD33 + 0.5
VIL Low-level input voltage USB (9) 0.8 V
OSC (10) 0.8
3.3-V LVTTL (1,2,3,4) 0.8
3.3-V I2C (8) –0.5 1.0
VDIS Differential Input Voltage USB (9) 200 mV
VICM Differential Cross Point Voltage USB (9) 0.8 2.5 V
VHYS Hysteresis (VT+-VT-) USB (9) 200 mV
3.3-V LVTTL (1,2,3,4) 400
3.3-V I2C (8) 300 550 600
VOH High-level output voltage USB (9) 2.8 V
1.8-V LVDS (7) 1.520
3.3-V LVTTL (1,2,3) IOH = Max Rated 2.7
VOL Low-level output voltage USB (9) 0.0 0.3 V
1.8-V LVDS (7) 0.880
3.3-V LVTTL (1,2,3) IOL = Max Rated 0.4
3.3-V I2C (8) IOL = 3 mA sink 0.4
VOD Output Differential Voltage 1.8-V LVDS (7) 0.065 0.440 V
IIH High-level input current USB (9) 200 µA
OSC (10) –10.0 10
3.3-V LVTTL (1-4) without Internal Pull Down VIH = VDD33 –10.0 10
3.3-V LVTTL (1-4) with Internal Pull Down VIH = VDD33 10.0 200.0
3.3-V I2C (8) VIH = VDD33 10.0
IIL Low-level input current USB (9) –10.0 10.0 µA
OSC (10) –10.0 10.0
3.3-V LVTTL (1-4) without Internal Pull Down VOH = VDD33 –10.0 10.0
3.3-V LVTTL (1-4) with Internal Pull Down VOH = VDD33 –10.0 –200
3.3-V I2C (8) VOH = VDD33 –10.0
IOH High-level output current USB (9) –19.1 mA
1.8-V LVDS (7) (VOD = 300mV) VO = 1.4 V 6.5
3.3-V LVTTL (1) VO = 2.4 V –4.0
3.3-V LVTTL (2) VO = 2.4 V –8.0
3.3-V LVTTL (3) VO = 2.4 V –12.0
IOL Low-level output current USB (9) 19.1 mA
1.8-V LVDS (7) (VOD = 300mV) VO = 1.0 V 6.5
3.3-V LVTTL (1) VO = 0.4 V 4.0
3.3-V LVTTL (2) VO = 0.4 V 8.0
3.3-V LVTTL (3) VO = 0.4 V 12.0
3.3-V I2C (8) 3.0
IOZ High-Impedance leakage current USB (9) –10 pF
LVDS (7) –10
3.3-V LVTTL (1,2,3) –10
3.3-V I2C (8) –10
CI Input capacitance USB (9) 11.84 17.07 pF
3.3-V LVTTL (1) 3.75 5.52
3.3-V LVTTL (2) 3.75 5.52
3.3-V LVTTL (4) 3.75 5.52
3.3-V I2C (8) 5.26 6.54
ICC11 Supply voltage, 1.1-V core power Normal Mode 1474 mA
ICC18 Supply voltage, 1.8-V power (LVDS I/O & Internal DRAM) Normal Mode 1005 mA
ICC33 Supply voltage, 3.3-V I/O power Normal Mode 33 mA
ICC11_PLLD Supply voltage, DMD PLL Digital Power (1.1-V) Normal Mode 4.4 6.2 mA
ICC11_PLLM1 Supply voltage, Master-LS Clock Generator PLL Digital power (1.1-V) Normal Mode 4.4 6.2 mA
ICC11_PLLM2 Supply voltage, Master-HS Clock Generator PLL Digital power (1.1-V) Normal Mode 4.4 6.2 mA
ICC18_PLLD Supply voltage, DMD PLL Analog Power (1.8 V) Normal Mode 8.0 10.2 mA
ICC18_PLLM1 Supply voltage, Master-LS Clock Generator PLL Analog power (1.8-V) Normal Mode 8.0 10.2 mA
ICC18_PLLM2 Supply voltage, Master-HS Clock Generator PLL Analog power (1.8-V) Normal Mode 8.0 10.2 mA
ICC11_PLLS Supply voltage, Video-2X PLL Analog Power (1.1-V) Normal Mode 2.9 mA
Total Power Normal Mode 3.73 W
The number inside each parenthesis or the I/O refers to the type defined in Table 1.