DLPS206 Data sheet

DLPS206 May 2021 DLPC7540

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

ZDC|676
- MPBGAP5

Thermal pad, mechanical data (Package|Pins)

Orderable Information

dlps206_oa

6.13 Power Supply and Reset Timing Requirements

PARAMETER			MIN	MAX	UNIT
t_RAMP-UP	Power supply ramp-up time.⁽¹⁾ Figure 6-5	Power supply ramp for each supply Ramp-up time: TOV × 10% to TOV × 90% TOV = Typical Operational Voltage	0.01	10	ms
t_{RAMP-UP-TOTAL}	Total power supply ramp-up time.⁽¹⁾	Total time within which the 1.15-V, 1.8-V, 1.21-V, and 3.3-V supplies must complete their ramp-up from the start of the 1.15-V ramp-up. Ramp-up time: TOV × 10% to TOV × 90% TOV = Typical Operational Voltage		100	ms
t_RAMP-DOWN	Power supply ramp-down time. ⁽¹⁾ Figure 6-5 Figure 6-6	Power supply ramp for each supply Ramp-down time: TOV × 90% to TOV × 10% TOV = Typical Operational Voltage	0	100	ms
t_{RAMP-DOWN-TOTAL}	Total power supply ramp-down time.⁽¹⁾	Total time within which the 1.15-V, 1.8-V, 1.21-V, and 3.3-V supplies must complete their ramp-down from the start of the 3.3-V ramp-up. Ramp-down time: TOV × 90% to TOV × 10% TOV = Typical Operational Voltage		100	ms
t_RUSD18	1.8-V Supply Ramp-up Start Delay ⁽²⁾ Figure 6-6	Delay from 1.15-V supply ramp start to 1.8-V supply ramp start.	See ⁽³⁾		ms
t_RUSD33	3.3-V Supply Ramp-up Start Delay ⁽²⁾ Figure 6-6	Delay from 1.15-V supply ramp start to 3.3-V supply ramp start	10	50	ms
t_RUSD12	1.21-V Supply Ramp-up Start Delay ⁽²⁾ Figure 6-6	Delay from 1.8-V supply ramp start to 1.21-V supply ramp start.	See ⁽⁴⁾		ms
t_RDSD18	1.8-V Supply Ramp-down Start Delay ⁽²⁾ Figure 6-6	Delay from 1.21-V supply ramp start to 1.8-V supply ramp start.	See ⁽⁵⁾		ms
t_RDSD115	1.15-V Supply Ramp-down Start Delay ⁽²⁾ Figure 6-6	Delay from 3.3-V supply ramp start to 1.15-V supply ramp start.	See⁽⁸⁾
t_EW	Early Warning Time Figure 6-8	PWRGOOD goes inactive low (as an early warning) prior to any power supply voltage going below the controller specification	500		µs
t_PH	Power Hold Time Figure 6-8	POSENSE remains active after PWRGOOD is disabled	500⁽⁹⁾		µs
t_w1	Pulse duration, in-active low, PWRGOOD Figure 6-7	PWRGOOD inactive time while POSENSE is active 50% to 50% reference points (signal)	4	1000 ⁽⁶⁾	µs
t_t1	Transition time, PWRGOOD t_t1 = t_ƒ1 and t_r1 Figure 6-7	Rise and Fall time for PWRGOOD 20% to 80% reference points (signal)		625	µs
t_w2	Pulse duration, in-active low, POSENSE Figure 6-8	POSENCE inactive time while PWRGOOD is inactive 50% to 50% reference points (signal)	100		ms
t_t2	Transition time, POSENSE t_t1 = t_ƒ1 and t_r1 Figure 6-8	Rise and Fall time for POSENSE ⁽⁷⁾ 20% to 80% reference points (signal)		25	µs
t_PSD	PWRGOOD Start Delay Figure 6-7	Time after rising edge of POSENSE before PWRGOOD effects DLPC7540 operation	51.5	60	ms
t_{PROJ_ON}	PROJ_ON fall time delay to PWRGOOD Figure 6-8	Fall Delay PROJ_ON 80% to PWRGOOD 80% fall time start	10		ms
t_REFCLKA	Time to stable REFCLKA Figure 6-7	Time to stable REFLCKA before POSENSE	See ⁽¹⁰⁾

(1) It is assumed that all 1.15-V supplies come from the same source, although some can have additional filtering before entering the DLPC7540. As such, it is expected these supplies to ramp together (aside from differences caused by filtering). This same expectation is true for the 1.21-V, 1.8-V, and 3.3-V supplies.

(2) The DLPC7540 has specific power supply sequencing requirements which are listed below, and which also include the timings specified in this table.

Power Up Order:
1. 1.15-V (Core, Analog) » 1.8-V (I/O, SCS) » 1.21-V (SCS)
2. 1.15-V (Core, Analog) » 3.3-V (I/O
Power Down Order:
1. 3.3-V (I/O) » 1.15-V (Core, Analog)
2. 1.21-V (SCS) » 1.8-V (I/O, SCS) » 1.15-V (Core, Analog)

(3) This delay requirement parameter is defined as the time between two events. The first event is the point where the 1.15-V power supply ramp-up is started, and the second event is when the 1.15-V supply ramp-up reaches 80% of TOV (at which point the 1.8-V supply can start its ramp-up). Because the occurrence of the second event depends on the specific design of the 1.15-V power supply, the designer must determine the specific delay time.

(4) This delay requirement parameter is defined as the time between two events. The first event is the point where the 1.8-V power supply ramp-up is started, and the second event is when the 1.8-V supply ramp-up reaches 80% of TOV (at which point the 1.21-V supply can start its ramp-up). Because the occurrence of the second event depends on the specific design of the 1.8-V power supply, the designer must determine the specific delay time.

(5) This delay requirement parameter is defined as the time between two events. The first event is the point where the 1.21-V power supply ramp-down is started, and the second event is when the 1.21-V supply ramp-down reaches 20% of TOV (at which point the 1.8-V supply can start its ramp-down). Because the occurrence of the second event depends on the specific design of the 1.21-V power supply, the designer must determine the specific delay time.

(6) This max value is only applicable if the 1.8-V power remains ON while PWRGOOD is inactive. Otherwise, there is no maximum limit.

(7) As long as noise on this signal is below the hysteresis threshold

(8) This delay requirement parameter is defined as the time between two events. The first event is the point where the 3.3-V power supply ramp-down is started, and the second event is when the 3.3-V supply ramp-down and 1.8-V supply ramp down reaches 10% of TOV (at which point the 1.15-V supply can start its ramp-down). Because the occurrence of the second event depends on the specific design of the 3.3V and 1.8-V power supply, the designer must determine the specific delay time.

(9) If PROJ_ON is used for power down then Power Hold Time (t_PH) is not required.

(10) This delay requirement parameter is defined by design of RECLKA oscillator. Stable clock must be provided before releasing POSENSE.

Figure 6-5 Power Supply Ramp Time

Figure 6-6 Power Supply Ramp Sequencing Profiles

Figure 6-7 Power Up Timing

Figure 6-8 Power Down Timing