DLPS037F October   2014  – June 2021 DLPC900

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  System Oscillators Timing Requirements (1)
    7. 6.7  Power-Up and Power-Down Timing Requirements
      1. 6.7.1 Power-Up
      2. 6.7.2 Power-Down
    8. 6.8  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    9. 6.9  JTAG Interface: I/O Boundary Scan Application Switching Characteristics
    10. 6.10 Programmable Output Clocks Switching Characteristics
    11. 6.11 Port 1 and 2 Input Pixel Interface Timing Requirements
    12. 6.12 Two Pixels Per Clock (48-Bit Bus) Timing Requirements
    13. 6.13 SSP Switching Characteristics
    14. 6.14 DMD Interface Switching Characteristics (1)
    15. 6.15 DMD LVDS Interface Switching Characteristics
    16. 6.16 Source Input Blanking Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DMD Configurations
      2. 7.3.2 Video Timing Input Blanking Specification
      3. 7.3.3 Board-Level Test Support
      4. 7.3.4 Two Controller Considerations
      5. 7.3.5 Memory Design Considerations
        1. 7.3.5.1 Flash Memory Optimization
        2. 7.3.5.2 Operating Modes
        3. 7.3.5.3 DLPC900 Memory Space
        4. 7.3.5.4 Minimizing Memory Space
        5. 7.3.5.5 Minimizing Board Size
          1. 7.3.5.5.1 Package Selection
          2. 7.3.5.5.2 Large Density Flash
            1. 7.3.5.5.2.1 Combining Two Chip-Selects with One 32-Megabyte Flash
              1. 7.3.5.5.2.1.1 Combining Three Chip-Selects with One 64-Megabyte Flash
            2. 7.3.5.5.2.2 Combining Three Chip-Selects with One 128-Megabyte Flash
        6. 7.3.5.6 Minimizing Board Space
        7. 7.3.5.7 Flash Memory
    4. 7.4 Device Functional Modes
      1. 7.4.1 Structured Light Application
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Two Controller Chipset
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 DLPC900 System Interfaces
            1. 8.2.1.2.1.1 Control Interface
            2. 8.2.1.2.1.2 Input Data Interfaces
            3. 8.2.1.2.1.3 DLPC900 System Output Interfaces
              1. 8.2.1.2.1.3.1 Illumination Interface
              2. 8.2.1.2.1.3.2 Trigger and Sync Interface
            4. 8.2.1.2.1.4 DLPC900 System Support Interfaces
              1. 8.2.1.2.1.4.1 Reference Clock and PLL
              2. 8.2.1.2.1.4.2 Program Memory Flash Interface
              3. 8.2.1.2.1.4.3 DMD Interface
      2. 8.2.2 Typical Single Controller Chipset
  9. Power Supply Recommendations
    1. 9.1 System Power Regulation
      1. 9.1.1 Power Distribution System
        1. 9.1.1.1 1.15-V System Power
        2. 9.1.1.2 1.8-V System Power
        3. 9.1.1.3 3.3-V System Power
    2. 9.2 System Environment and Defaults
      1. 9.2.1 DLPC900 System Power-Up and Reset Default Conditions
    3. 9.3 System Power-Up Sequence
      1. 9.3.1 Power-On Sense (POSENSE) Support
      2. 9.3.2 Power Good (PWRGOOD) Support
      3. 9.3.3 5-V Tolerant Support
    4. 9.4 System Reset Operation
      1. 9.4.1 Power-Up Reset Operation
      2. 9.4.2 System Reset Operation
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General PCB Recommendations
      2. 10.1.2  PCB Layout Guidelines for Internal Controller PLL Power
      3. 10.1.3  PCB Layout Guidelines for Quality Video Performance
      4. 10.1.4  Recommended MOSC Crystal Oscillator Configuration
      5. 10.1.5  Spread Spectrum Clock Generator Support
      6. 10.1.6  GPIO Interface
      7. 10.1.7  General Handling Guidelines for Unused CMOS-Type Pins
      8. 10.1.8  DMD Interface Considerations
        1. 10.1.8.1 Flex Connector Plating
      9. 10.1.9  PCB Design Standards
      10. 10.1.10 Signal Layers
      11. 10.1.11 Trace Widths and Minimum Spacing
      12. 10.1.12 Trace Impedance and Routing Priority
      13. 10.1.13 Power and Ground Planes
      14. 10.1.14 Power Vias
      15. 10.1.15 Decoupling
      16. 10.1.16 Fiducials
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
      3. 11.1.3 DEFINITIONS - Video Timing Parameters
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Revision History

Changes from Revision E (March 2020) to Revision F ( June 2021)

  • Updated the numbering format for tables, figures, and cross-references throughout the documentGo
  • Updated terminology to primary and secondary.Go
  • Updated "DLP LightCrafter 9000 EVM" to "DLP LightCrafter Dual DLPC900 Evaluation Module (EVM)"Go
  • Added 10 kΩ pulldown resistor requirement to the FAULT-STATUS pin description.Go
  • Updated H22, T22, and U23 to be Flash Address line extensionsGo
  • Updated terminology to primary and secondary.Go
  • DLPC900A ESD Human body model (HBM) and Charged device model (CDM) information added.Go
  • Updated terminology to primary and secondary.Go
  • Updated section to include DLP500YX and DLP670S DMDs.Go
  • Updated terminology to primary and secondary.Go
  • Included DLP500YX and DLP670S DMDs in sectionGo
  • Modified section to update DLPC900 Memory Space diagram and add new information about design and layout for larger flash devices up to 128-Megabytes.Go
  • Updated Section 7.3.5.5.2.2 to "Combining Three Chip Selects with One 128-Megabyte Flash" Go
  • Changed "LightCrafter 6500 and the LightCrafter 9000" to "Single DLPC900 Evaluation Module" and "Dual DLPC900 Evaluation Module".Go
  • Added 2-Gigabit Flash Memory device to Micron and Spansion devices listGo
  • Updated link to DLP® LightCrafter™ Single DLPC900 Evaluation Module (EVM) User's Guide (DLPU101) or DLP® LightCrafter™ Dual DLPC900 Evaluation Module (EVM) User's Guide (DLPU102)Go
  • Updated Minimum Exposure in Any Pattern Mode table to include DLP500YX and DLP670S DMDsGo
  • Updated Minimum Exposures for Number of Active DMD Blocks table to include DLP500YX and DLP670S DMDsGo
  • Updated Section to include DLP500YX and DLP670S DMDs.Go
  • Updated terminology to primary and secondary. Go
  • Updated section to include DLP500YX and DLP670S DMDs. Go
  • Updated Boot Flash Memory Layout to reflect updated flash design.Go
  • Updated terminology to primary and secondaryGo
  • Updated Related Documents TableGo

Changes from Revision D (March 2019) to Revision E (March 2020)

  • Changed DMD references to general device numbers to remove revision dependencies Go
  • Generalized device number to remove revision dependencies Go
  • Updated Section 11.1.1 section to show additional identification for revisionsGo
  • Updated Section 11.1.2 section Go

Changes from Revision C (October 2016) to Revision D (March 2019)

  • Changed "Pre-loaded" to "using Pre-stored Pattern Mode"Go
  • Deleted Stores up to 400 1-Bit Binary or 50 8-Bit Grayscale Patterns from 128 Mbit Internal DRAMGo
  • Changed "MB" to "Mbit" for DRAM and External Flash throughout the documentGo
  • Changed Quality Control to Automatic Optical Inspection in Applications Go
  • Added Additive Manufacturing Go
  • Added Heads Up Display in Applications Go
  • Updated RθJC description from 'Junction-to-air thermal resistance' to 'Junction-to-case thermal resistance'Go
  • Changed Firmware compatibility information to version 4 for all DMDsGo
  • Deleted Power-Down Method "A" to have one MethodGo
  • Changed the DMD Full-Bus Connections reference link from the DLPC900 Programmer's Guide to the DLP LightCrafter 6500 & 9000 EVM User's GuideGo
  • Added note clarifying number of patterns storable in External Flash memory. Go
  • Changed Section 11.1.2 Lines 3 - 5 to TI proprietary informationGo

Changes from Revision B (September 2016) to Revision C (October 2016)

  • Updated description of POSENSE and PWRGOOD.Go
  • Changed Reset Timing Requirements to Power-Up and Power-Down Timing Requirements.Go
  • Added power-up and power-down requirements for revision "B" DMDs.Go
  • Updated the description of Power-On Sense (POSENSE) Support and added cross-reference to Power-Up and Power-Down Timing Requirements.Go
  • Updated the description of Power Good (PWRGOOD) Support and added cross-reference to Power-Up and Power-Down Timing Requirements.Go

Changes from Revision A (August 2015) to Revision B (September 2016)

  • Changed "DLP9500" to "DLP9000"Go
  • Changed number of patterns for 48Mbit External FlashGo
  • Added "or 50 8-Bit Grayscale Patterns"Go
  • Added Memory Design Considerations section Go
  • Changed "done" to "performed"Go
  • Changed sentence about "four operating modes"Go
  • Changed "minimized" to "optimized for"Go
  • Changed sentences re: reduced PCB size and reduced costs and power supply requirementsGo
  • Added (EVMs from TIGo
  • Changed "acceding" to "ascending"Go
  • Changed reference to point to Go
  • Changed "The LightCrafter 6500 and 9000 GUI software"Go
  • Corrected Minimum Exposures for Number of Active DMD Blocks Reserved hex numbers to 0xF97FFFFFGo
  • Changed figure referenced "When the memory requirement is greater than 16 Mbit but less than 32 Mbit"Go
  • Deleted "saving valuable board space"Go
  • Deleted "Fig. 25 shows three examples how not to mix different densities." Go
  • Deleted Figure 25Go
  • Added paragraph at beginning of "Flash Memory"Go
  • Changed "EVM" to "LightCrafter 6500 and the LightCrafter 9000."Go
  • Added "(pre-stored pattern mode, pattern on-the-fly mode, or video pattern mode),"Go
  • Added "pattern on-the-fly mode."Go
  • Added "and pattern on-the-fly modes"Go
  • Changed to "In video pattern mode, pre-stored pattern mode, and pattern on-the-fly mode,"Go
  • Added "For faster 8-bit pattern speeds, . . ."Go
  • Added link to "DLP6500 & 9000 EVM User's Guide"Go

Changes from Revision * (October 2014) to Revision A (August 2015)

  • Corrected the width of the input pixel ports to 24-bitsGo
  • Added I/O Type and Subscript Definition tableGo
  • Corrected maximum port width of Ports 1 and 2 in table noteGo
  • Updated ESD Ratings table title and value columnGo
  • ESD sensitivity machine model was removedGo
  • Added note to clarify that Ports 1 and 2 are used as 24-bit busesGo
  • Changed section title to correct bus size to 48-bitsGo
  • Removed references to 30-bit RGB videoGo
  • Corrected minor typosGo
  • Corrected video pattern mode timing diagram and descriptionGo
  • Corrected pre-stored pattern mode timing diagram and descriptionGo
  • Corrected pre-stored pattern mode 3 pattern example diagram and descriptionGo
  • Updated Boot Flash Memory Layout image to reflect firmware version 2.0Go
  • Added note about firmware components.Go
  • Corrected video data interface size to 24-bitsGo
  • Corrected video mode port maximum size to 24 bitsGo
  • Corrected P1 and P2 signal description regarding 24-bit bus widthGo
  • Corrected spacing and formattingGo
  • Corrected minor typoGo
  • Changed the number of P1 and P2 lines to reflect 24 bit-widthGo