DLPS037F October 2014 – June 2021 DLPC900
PWRGOOD cannot be used as an early warning signal. DMDs require an enhanced power down where the DLPC900 performs a sequence of memory loads to the DMD followed by the mirror park instruction so that the mirrors end up in an un-landed state.
There are two scenarios to consider when powering down DMDs supported by the DLPC900. Figure 6-3 shows a power distribution layout for a typical system, which provides the mechanisms for both scenarios.
The first scenario is an anticipated power down, which is during a typical power down of the system. Figure 6-4 shows a timing diagram where an external host sends a power down command to the microprocessor (µP). The µP must send a Power Standby command to the DLPC900. The DLPC900 then performs the necessary power down sequence on the DMD. The power can be safely removed once the minimum tePH is met.
The second scenario is an unanticipated power loss. In this case a power loss detection circuit must provide a means of triggering a power loss. Figure 6-5 shows a timing diagram where the power loss detection circuit detects a power loss and asserts PWRLOSS to the µP. The µP must send a Power Standby command to the DLPC900. The DLPC900 then performs the necessary power down sequence on the DMD. The power supplies can be allowed to drop below their specifications once the minimum tePH is met.
Refer to the DLPC900 Programmer's Guide for a description of the Power Standby command.