DLPS065D September   2015  – December 2021 DLPR910

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Supply Voltage Requirements for Power-On Reset and Power-Down
    7. 6.7 Timing Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Data Interface
        1. 7.3.1.1 Data Outputs
        2. 7.3.1.2 Configuration Clock Input
        3. 7.3.1.3 Output Enable and Reset
        4. 7.3.1.4 Chip Enable
        5. 7.3.1.5 Configuration Pulse
        6. 7.3.1.6 Revision Selection
    4. 7.4 Device Functional Modes
      1.      26
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Compatibility
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

Pin Configuration and Functions

GUID-5F8089D8-23A6-4401-A8AC-7FAA989FC7A9-low.gifFigure 5-1 YVA Package48-Pin DSBGATop View
Table 5-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
GNDA1GGround
GNDA2GGround
OE/ RESETA3I/OOutput Enable/ RESET (Open-Drain I/O). When Low, this input holds the address counter reset and the DATA and CLKOUT outputs are placed in a high-impedance state. This is a bidirectional open-drain pin that is held Low while the PROM completes the internal power-on reset sequence. Polarity is not programmable. Pin must be pulled High using an external 4.7-kΩ pull-up to VCCO.
DNCA4Do Not Connect. Leave unconnected.
D6A5Do Not Connect. Leave unconnected.
D7A6Do Not Connect. Leave unconnected.
VCCINTB1PPositive 1.8-V supply voltage for internal logic.
VCCOB2PPositive 3.3-V and 1.8-V supply voltage connected to the output voltage drivers and internal buffers.
CLKB3IConfiguration clock input. Each rising edge on the CLK input increments the internal address counter. Pin must be pulled High and Low using an external 100-Ω pull-up to VCCO and an external 100-Ω pull-down to Ground. Place resistors close to pin.
CEB4IChip Enable Input. When CE is High, the device is put into low-power standby mode, the address counter is reset, and the DATA and CLKOUT outputs are placed in a high impedance state. Pin must be pulled High using an external 4.7-kΩ pull-up to VCCO.
D5B5Do Not Connect. Leave unconnected.
GNDB6GGround
BUSYC1Do Not Connect. Leave unconnected.
CLKOUTC2Do Not Connect. Leave unconnected.
DNCC3Do Not Connect. Leave unconnected.
DNCC4Do Not Connect. Leave unconnected.
D4C5Do Not Connect. Leave unconnected.
VCCOC6PPositive 3.3-V and 1.8-V supply voltage connected to the output voltage drivers and internal buffers.
CFD1IConfiguration pin. The CF pin must be pulled High using an external 4.7-kΩ pull-up to VCCO. Selects serial mode configuration.
CEOD2Do Not Connect. Leave unconnected.
DNCD3Do Not Connect. Leave unconnected.
DNCD4Do Not Connect. Leave unconnected.
D3D5Do Not Connect. Leave unconnected.
VCCOD6PPositive 3.3-V and 1.8-V supply voltage connected to the output voltage drivers and internal buffers.
VCCINTE1PPositive 1.8-V supply voltage for internal logic.
TMSE2IJTAG Mode Select Input. TMS has an internal 50-kΩ resistive pull-up to VCCJ.
DNCE3Do Not Connect. Leave unconnected.
DNCE4Do Not Connect. Leave unconnected.
DNCE5Do Not Connect. Leave unconnected.
TDOE6OJTAG Serial Data Output. TDO has an internal 50-kΩ resistive pull-up to VCCJ.
GNDF1GGround
DNCF2Do Not Connect. Leave unconnected.
DNCF3Do Not Connect. Leave unconnected.
DNCF4Do Not Connect. Leave unconnected.
GNDF5GGround
GNDF6GGround
TDIG1IJTAG Serial Data Input. TDI has an internal 50k-Ω resistive pull-up to VCCJ.
DNCG2Do Not Connect. Leave unconnected.
REV_SEL0G3IRevision Select [1:0] Inputs. When the EN_EXT_SEL is Low, the Revision Select pins are used to select the design revision to be enabled. The Revision Select [1:0] inputs have an internal 50-kΩ resistive pull-up to VCCO. The REV_SEL0 pin must be pulled Low using an external 4.7-kΩ pull-down to Ground. The REV_SEL1 pin must be pulled Low using an external 4.7-kΩ pull-down to Ground.
REV_SEL1G4I
VCCOG5PPositive 3.3-V and 1.8-V supply voltage connected to the output voltage drivers and internal buffers.
VCCINTG6PPositive 1.8-V supply voltage for internal logic.
GNDH1GGround
VCCJH2PPositive 3.3-V JTAG I/O supply voltage connected to the TDO output voltage driver and TCK, TMS and TDI input buffers.
TCKH3IJTAG Clock Input. This pin is the JTAG test clock. It sequences the TAP controller and all the JTAG test and programming electronics.
EN_EXT_SELH4IExternal Selection Input. EN_EXT_SEL has an internal 50-kΩ resistive pull- up to VCCO. The EN_EXT_SEL pin must be connected to Ground.
D1H5Do Not Connect. Leave unconnected.
D0H6ODATA output pin to provide data for configuring the DLPC910 in serial mode.
P = Power, G = Ground, I = Input, O = Output