DLPS065D September   2015  – December 2021 DLPR910

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Supply Voltage Requirements for Power-On Reset and Power-Down
    7. 6.7 Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Data Interface
        1. 7.3.1.1 Data Outputs
        2. 7.3.1.2 Configuration Clock Input
        3. 7.3.1.3 Output Enable and Reset
        4. 7.3.1.4 Chip Enable
        5. 7.3.1.5 Configuration Pulse
        6. 7.3.1.6 Revision Selection
    4. 7.4 Device Functional Modes
      1.      26
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Compatibility
      2. 11.1.2 Device Nomenclature
      3. 11.1.3 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

7.3.1.4 Chip Enable

The CE input is asserted by the DLPC910 controller to enable the Data (D0) and CLKOUT outputs. When CE is held high, the DLPR910 device address counter is reset, and the Data and CLKOUT outputs are placed in high-impedance states.