SNLS505F July   2016  – June 2021 DP83822H , DP83822HF , DP83822I , DP83822IF

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements, Power-Up Timing
    7. 7.7  Timing Requirements, Power-Up With Unstable XI Clock
    8. 7.8  Timing Requirements, Reset Timing
    9. 7.9  Timing Requirements, Serial Management Timing
    10. 7.10 Timing Requirements, 100 Mbps MII Transmit Timing
    11. 7.11 Timing Requirements, 100 Mbps MII Receive Timing
    12. 7.12 Timing Requirements, 10 Mbps MII Transmit Timing
    13. 7.13 Timing Requirements, 10 Mbps MII Receive Timing
    14. 7.14 Timing Requirements, RMII Transmit Timing
    15. 7.15 Timing Requirements, RMII Receive Timing
    16. 7.16 Timing Requirements, RGMII
    17. 7.17 Normal Link Pulse Timing
    18. 7.18 Auto-Negotiation Fast Link Pulse (FLP) Timing
    19. 7.19 10BASE-Te Jabber Timing
    20. 7.20 100BASE-TX Transmit Latency Timing
    21. 7.21 100BASE-TX Receive Latency Timing
    22. 7.22 Timing Diagrams
    23. 7.23 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Energy Efficient Ethernet
        1. 8.3.1.1 EEE Overview
        2. 8.3.1.2 EEE Negotiation
      2. 8.3.2 Wake-on-LAN Packet Detection
        1. 8.3.2.1 Magic Packet Structure
        2. 8.3.2.2 Magic Packet Example
        3. 8.3.2.3 Wake-on-LAN Configuration and Status
      3. 8.3.3 Start of Frame Detect for IEEE 1588 Time Stamp
      4. 8.3.4 Clock Output
    4. 8.4 Device Functional Modes
      1. 8.4.1  MAC Interfaces
        1. 8.4.1.1 Media Independent Interface (MII)
        2. 8.4.1.2 Reduced Media Independent Interface (RMII)
        3. 8.4.1.3 Reduced Gigabit Media Independent Interface (RGMII)
      2. 8.4.2  Serial Management Interface
        1. 8.4.2.1 Extended Register Space Access
        2. 8.4.2.2 Write Address Operation
        3. 8.4.2.3 Read Address Operation
        4. 8.4.2.4 Write (No Post Increment) Operation
        5. 8.4.2.5 Read (No Post Increment) Operation
        6. 8.4.2.6 Write (Post Increment) Operation
        7. 8.4.2.7 Read (Post Increment) Operation
        8. 8.4.2.8 Example Write Operation (No Post Increment)
        9. 8.4.2.9 Example Read Operation (No Post Increment)
      3. 8.4.3  100BASE-TX
        1. 8.4.3.1 100BASE-TX Transmitter
          1. 8.4.3.1.1 Code-Group Encoding and Injection
          2. 8.4.3.1.2 Scrambler
          3. 8.4.3.1.3 NRZ to NRZI Encoder
          4. 8.4.3.1.4 Binary to MLT-3 Converter
        2. 8.4.3.2 100BASE-TX Receiver
      4. 8.4.4  100BASE-FX
        1. 8.4.4.1 100BASE-FX Transmit
        2. 8.4.4.2 100BASE-FX Receive
      5. 8.4.5  10BASE-Te
        1. 8.4.5.1 Squelch
        2. 8.4.5.2 Normal Link Pulse Detection and Generation
        3. 8.4.5.3 Jabber
        4. 8.4.5.4 Active Link Polarity Detection and Correction
      6. 8.4.6  Auto-Negotiation (Speed / Duplex Selection)
      7. 8.4.7  Auto-MDIX Resolution
      8. 8.4.8  Loopback Modes
        1. 8.4.8.1 Near-End Loopback
        2. 8.4.8.2 MII Loopback
        3. 8.4.8.3 PCS Loopback
        4. 8.4.8.4 Digital Loopback
        5. 8.4.8.5 Analog Loopback
        6. 8.4.8.6 Far-End (Reverse) Loopback
      9. 8.4.9  BIST Configurations
      10. 8.4.10 Cable Diagnostics
        1. 8.4.10.1 TDR
      11. 8.4.11 Fast Link Down Functionality
    5. 8.5 Programming
      1. 8.5.1 Hardware Bootstrap Configurations
      2. 8.5.2 LED Configuration
      3. 8.5.3 PHY Address Configuration
    6. 8.6 Register Maps
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TPI Network Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Fiber Network Circuit
        1. 9.2.2.1 Design Requirements
          1. 9.2.2.1.1 Clock Requirements
            1. 9.2.2.1.1.1 Oscillator
            2. 9.2.2.1.1.2 Crystal
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 MII Layout Guidelines
          2. 9.2.2.2.2 RMII Layout Guidelines
          3. 9.2.2.2.3 RGMII Layout Guidelines
          4. 9.2.2.2.4 MDI Layout Guidelines
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Characteristics
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Signal Traces
      2. 11.1.2 Return Path
      3. 11.1.3 Transformer Layout
        1. 11.1.3.1 Transformer Recommendations
      4. 11.1.4 Metal Pour
      5. 11.1.5 PCB Layer Stacking
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Register Maps

In the register definitions under the “TYPE” heading, the following definitions apply:

    CORClear on Read
    StrapDefault value loads from bootstrap pin after reset
    LHLatched high and held until read
    LLLatched low and held until read
    RORead Only Access
    RO/CORRead Only, Clear on Read
    RO/PRead Only, Permanently set to a default value
    RWRead Write access
    RW/SCRead Write access, Self Clearing bit
    SCRegister sets on event occurrence and Self-Clears when event ends
Table 8-14 0x0000 Basic Mode Control Register (BMCR)
BITNAMETYPEDEFAULTFUNCTION
15ResetRW, SC0PHY Software Reset:
1 = Initiate software Reset / Reset in Progress
0 = Normal Operation

Writing a 1 to this bit resets the PHY PCS registers. When the reset operation is done, this bit is cleared to 0 automatically. PHY Vendor Specific registers (with MMD = 1F) will not be cleared.
Straps are not re-latched with this reset. Straps are re-latched only during power up and pin reset.

14MII LoopbackRW0MII Loopback:
1 = MII Loopback enabled
0 = Normal Operation

When MII loopback mode is activated, the transmitted data presented on MII TXD is looped back to MII RXD internally.

13Speed SelectionRW, Strap1Speed Select:
1 = 100 Mbps
0 = 10 Mbps

When Auto-Negotiation is disabled (bit[12] = 0 in Register 0x0000), writing to this bit allows the port speed to be selected.

12Auto-Negotiation EnableRW, Strap1Auto-Negotiation Enable:
1 = Enable Auto-Negotiation
0 = Disable Auto-Negotiation

If Auto-Negotiation is disabled, bit[8] and bit[13] of this register determine the port speed and duplex mode.

11IEEE Power DownRW0Power Down:
1 = IEEE Power Down
0 = Normal Operation

The PHY is powered down after this bit is set. Only register access is enabled during this power down condition. To control the power down mechanism, this bit is OR'ed with the input from the INT/PWDN_N pin. When the active low INT/PWDN_N is asserted, this bit is set.
Programmed register are not reset to default in power down. Since all state machines undergo reset so status bits (RO) may show a change in value.

10IsolateRW0Isolate:
1 = Isolates the port from the MII with the exception of the SMI
0 = Normal Operation
9Restart Auto-NegotiationRW, SC0Restart Auto-Negotiation:
1 = Restarts Auto-Negotiation
0 = Normal Operation

If Auto-Negotiation is disabled (bit[12] = 0), bit[9] is ignored. This bit is self-clearing and will return a value of 1 until Auto-Negotiation is initiated, whereupon it will self-clear. Operation of the Auto-Negotiation process is not affected by the management entity clearing this bit.

8Duplex ModeRW, Strap1Duplex Mode:
1 = Full-Duplex
0 = Half-Duplex

When Auto-Negotiation is disabled, writing to this bit allows the port Duplex capability to be selected.

7Collision TestRW0Collision Test:
1 = Enable COL Signal Test
0 = Normal Operation

When set, this bit causes the COL signal to be asserted in response to the assertion of TX_EN within 512 bit times. The COL signal is de-asserted within 4 bit times in response to the de-assertion to TX_EN.

6:0ReservedRO0Reserved
Table 8-15 0x0001 Basic Mode Status Register (BMSR)
BITNAMETYPEDEFAULTFUNCTION
15100Base-T4RO0100Base-T4 Capable:
This protocol is not available. Always reads as 0.
14100Base-TX Full-DuplexRO1100Base-TX Full-Duplex Capable:
1 = Device able to perform Full-Duplex 100Base-TX
0 = Device not able to perform Full-Duplex 100Base-TX
13100Base-TX Half-DuplexRO1100Base-TX Half-Duplex Capable:
1 = Device able to perform Half-Duplex 100Base-TX
0 = Device not able to perform Half-Duplex 100Base-TX
1210Base-Te Full-DuplexRO110Base-Te Full-Duplex Capable:
1 = Device able to perform Full-Duplex 10Base-Te
0 = Device not able to perform Full-Duplex 10Base-Te
1110Base-Te Half-DuplexRO110Base-Te Half-Duplex Capable:
1 = Device able to perform Half-Duplex 10Base-Te
0 = Device not able to perform Half-Duplex 10Base-Te
10:7ReservedRO0Reserved
6SMI Preamble SuppressionRO1Preamble Suppression Capable:
1 = Device able to perform SMI transaction with preamble suppressed
0 = Device not able to perform SMI transaction with preamble suppressed

If this bit is set to 1, 32-bits of preamble needed only once after reset, invalid opcode or invalid turnaround.

5Auto-Negotiation CompleteRO0Auto-Negotiation Complete:
1 = Auto-Negotiation process completed
0 = Auto Negotiation process not completed (either still in process, disabled or reset)
4Remote FaultRO, LH0Remote Fault:
1 = Remote fault condition detected
0 = No remote fault condition detected

Far End Fault indication or notification from Link Partner of Remote Fault. This bit is cleared on read or reset.

3Auto-Negotiation AbilityRO1Auto-Negotiation Ability:
1 = Device is able to perform Auto-Negotiation
0 = Device is not able to perform Auto-Negotiation
2Link StatusRO, LL0Link Status:
1 = Valid link established (for either 10 Mbps or 100 Mbps operation)
0 = Link not established
If link goes low anytime, this bit value will read 0 on first read after link down event. Will get cleared to 1 only if status is read second time after link-up.
1Jabber DetectRO, LH0Jabber Detect:
1 = Jabber condition detected
0 = No jabber condition detected

This bit only has meaning for 10Base-Te operation.

0Extended CapabilityRO1Extended Capability:
1 = Extended register capabilities
0 = Basic register set capabilities only
Table 8-16 0x0002 PHY Identifier Register #1 (PHYIDR1)
BITNAMETYPEDEFAULTFUNCTION
15:0Organizationally Unique Identifier Bits 21:6RO0010 0000 0000 0000
Table 8-17 0x0003 PHY Identifier Register #2 (PHYIDR2)
BITNAMETYPEDEFAULTFUNCTION
15:10Organizationally Unique Identifier Bits 5:0RO1010 00
9:4Model NumberRO10 0100Vendor Model Number:
The six bits of vendor model number are mapped from bits [9] to [4]
3:0Revision NumberRO0000Model Revision Number:
Four bits of the vendor model revision number are mapped from bits [3:0]. This field is incremented for all major device changes.
Table 8-18 0x0004 Auto-Negotiation Advertisement Register (ANAR)
BITNAMETYPEDEFAULTFUNCTION
15Next PageRW0Next Page Indication:
1 = Next Page Transfer desired
0 = Next Page Transfer not desired
14ReservedRO0Reserved
13Remote FaultRW0Remote Fault:
1 = Advertises that this device has detected a Remote Fault
0 = No Remote Fault detected
12ReservedRO0Reserved
11Asymmetric PauseRW0Asymmetric Pause Support For Full-Duplex Links:
1 = Advertise asymmetric pause ability
0 = Do not advertise asymmetric pause ability
10PauseRW0Pause Support for Full-Duplex Links:
1 = Advertise pause ability
0 = Do not advertise pause ability
9100Base-T4RO0100Base-T4 Support:
1 = Advertise 100Base-T4 ability
0 = Do not advertise 100Base-T4 ability
8100Base-TX Full-DuplexRW, Strap1100Base-TX Full-Duplex Support:
1 = Advertise 100Base-TX Full-Duplex ability
0 = Do not advertise 100Base-TX Full-Duplex ability
7100Base-TX Half-DuplexRW, Strap1100Base-TX Half-Duplex Support:
1 = Advertise 100Base-TX Half-Duplex ability
0 = Do not advertise 100Base-TX Half-Duplex ability
610Base-Te Full-DuplexRW, Strap110Base-Te Full-Duplex Support:
1 = Advertise 10Base-Te Full-Duplex ability
0 = Do not advertise 10Base-Te Full-Duplex ability
510Base-Te Half-DuplexRW, Strap110Base-Te Half-Duplex Support:
1 = Advertise 10Base-Te Half-Duplex ability
0 = Do not advertise 10Base-Te Half-Duplex ability
4:0Selector FieldRW0 0001Protocol Selection Bits:
Technology selector field (IEEE802.3u <00001>)
Table 8-19 0x0005 Auto-Negotiation Link Partner Ability Register (ANLPAR)
BITNAMETYPEDEFAULTFUNCTION
15Next PageRO0Next Page Indication:
1 = Link partner desires Next Page Transfer
0 = Link partner does not desire Next Page Transfer
14AcknowledgeRO0Acknowledge:
1 = Link partner acknowledges reception of link code word
0 = Link partner does not acknowledge reception of link code word
13Remote FaultRO0Remote Fault:
1 = Link partner advertises remote fault event detection
0 = Link partner does not advertise remote fault event detection
12ReservedRO0Reserved
11Asymmetric PauseRO0Asymmetric Pause:
1 = Link partner advertises asymmetric pause ability
0 = Link partner does not advertise asymmetric pause ability
10PauseRO0Pause:
1 = Link partner advertises pause ability
0 = Link partner does not advertise pause ability
9100Base-T4RO0100Base-T4 Support:
1 = Link partner advertises 100Base-T4 ability
0 = Link partner does not advertise 100Base-T4 ability
8100Base-TX Full-DuplexRO0100Base-TX Full-Duplex Support:
1 = Link partner advertises 100Base-TX Full-Duplex ability
0 = Link partner does not advertise 100Base-TX Full-Duplex ability
7100Base-TX Half-DuplexRO0100Base-TX Half-Duplex Support:
1 = Link partner advertises 100Base-TX Half-Duplex ability
0 = Link partner does not advertise 100Base-TX Half-Duplex ability
610Base-Te Full-DuplexRO010Base-Te Full-Duplex Support:
1 = Link partner advertises 10Base-Te Full-Duplex ability
0 = Link partner does not advertise 10Base-Te Full-Duplex ability
510Base-Te Half-DuplexRO010Base-Te Half-Duplex Support:
1 = Link partner advertises 10Base-Te Half-Duplex ability
0 = Link partner does not advertise 10Base-Te Half-Duplex ability
4:0Selector FieldRO0 0000Protocol Selection Bits:
Technology selector field (IEEE802.3 <00001>)
Table 8-20 0x0006 Auto-Negotiation Expansion Register (ANER)
BITNAMETYPEDEFAULTFUNCTION
15:5ReservedRO0Reserved
4Parallel Detection FaultRO, LH0Parallel Detection Fault:
1 = A fault has been detected during the parallel detection process
0 = No fault detected
3Link Partner Next Page AbleRO0Link Partner Next Page Ability:
1 = Link partner is able to exchange next pages
0 = Link partner is not able to exchange next pages
2Local Device Next Page AbleRO1Next Page Ability:
1 = Local device is able to exchange next pages
0 = Local device is not able to exchange next pages
1Page ReceivedRO, LH0Link Code Word Page Received:
1 = A new page has been received
0 = A new page has not been received
0Link Partner Auto-Negotiation AbleRO0Link Partner Auto-Negotiation Ability:
1 = Link partner supports Auto-Negotiation
0 = Link partner does not support Auto-Negotiation
Table 8-21 0x0007 Auto-Negotiation Next Page Register (ANNPTR)
BITNAMETYPEDEFAULTFUNCTION
15Next PageRW0Next Page Indication:
1 = Advertise desire to send additional next pages
0 = Do not advertise desire to send additional next pages
14ReservedRO0Reserved
13Message PageRW1Message Page:
1 = Current page is a message page
0 = Current page is an unformatted page
12Acknowledge 2RW0Acknowledge2:
1 = Will comply with message
0 = Cannot comply with message

Acknowledge2 is used by the next page function to indicate that Local Device has the ability to comply with the message received.

11ToggleRO0Toggle:
1 = Toggle bit in previously transmitted Link Code Word was 0
0 = Toggle bit in previously transmitted Link Code Word was 1

Toggle is used by the Arbiitration function within Auto-Negotiation to synchronize with the Link Parnter during Next Page exchange. This bit always takes the opposite value of the Toggle bit in the previously exchanged Link Code Word.

10:0CODERW000 0000 0001This field represents the code field of the next page transmission. If the Message Page bit is set (bit [13] of this register), then the code is interpreted as a Message Page, as defined in annex 28C of IEEE 802.3u. Otherwise, the code is interperated as an Unformatted Page, and the interpretation is application specific.

The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE 802.3u.

Table 8-22 0x0008 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
BITNAMETYPEDEFAULTFUNCTION
15Next PageRO0Next Page Indication:
1 = Advertise desire to send additional next pages
0 = Do not advertise desire to send additional next pages
14AcknowledgeRO0Acknowledge:
1 = Link partner acknowledges reception of link code word
0 = Link partner does not acknowledge reception of link code work
13Message PageRO0Message Page:
1 = Current page is a message page
0 = Current page is an unformatted page
12Acknowledge 2RO0Acknowledge2:
1 = Will comply with message
0 = Cannot comply with message

Acknowledge2 is used by the next page function to indicate that Local Device has the ability to comply with the message received.

11ToggleRO0Toggle:
1 = Toggle bit in previously transmitted Link Code Word was 0
0 = Toggle bit in previously transmitted Link Code Word was 1

Toggle is used by the Arbiitration function within Auto-Negotiation to synchronize with the Link Parnter during Next Page exchange. This bit always takes the opposite value of the Toggle bit in the previously exchanged Link Code Word.

10:0Message/ Unformatted FieldRO0 0000 0000This field represents the code field of the next page transmission. If the Message Page bit is set (bit 13 of this register), then the code is interpreted as a Message Page, as defined in annex 28C of IEEE 802.3u. Otherwise, the code is interperated as an Unformatted Page, and the interpretation is application specific.

The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE 802.3u.

Table 8-23 0x0009 Control Register #1 (CR1)
BITNAMETYPEDEFAULTFUNCTION
15:10ReservedRO0Reserved
9RMII Enhanced ModeRW0RMII Enhanced Mode:
1 = Enable RMII Enhanced Mode
0 = RMII operated in normal mode

In normal RMII mode, if the line is not idle, CRS_DV goes high. As soon as the False Carrier is detected, RX_ER is asserted and RXD is set to "2" (0010). This situation remains for the duration of the receive event. While in enhanced mode, CRS_DV is disqualified and de-asserted when the False Carrier is detected. This status also remains for the duration of the receive event. In addition, in normal mode, the start of the packet is intact. Each symbol error is indicatied by setting RX_ER high. The data on RXD is replaced with "1" starting with the first symbol error. While in enhanced mode, the CRS_DV is de-asserted with the first symbol error.

8TDR Auto-RunRW0TDR Auto-Run at Link Down:
1 = Enable execution of TDR procedure after link down event
0 = Disable automatic execution of TDR
7Link Loss RecoveryRW0Link Loss Recovery:
1 = Enable Link Loss Recovery mechanism
0 = Normal Link Loss operation

This mode allows recovery from short interference and continue to hold the link up for a few additional mSec until the short interference is gone and the signal is OK. Under Normal Link Loss operation, Link status will go down approximately 250μs from signal loss.

6Fast Auto MDIXRW0Fast Auto-MDIX:
1 = Enable Fast Auto-MDIX
0 = Normal Auto-MDIX

If both link partners are configured to work in Force 100Base-TX mode (Auto-Negotiation disabled), this mode enables Automatic MDI/MDIX resolution in a shortened time.

5Robust Auto MDIXRW0Robust Auto-MDIX:
1 = Enable Robust Auto-MDIX
0 = Disable Auto-MDIX

If link partners are configured for operational modes that are not supported by normal Auto-MDIX, Robust Auto-MDIX allows MDI/MDIX resolution and prevents deadlock.

When the DP83822 is strapped for 100 Mbps operation with Auto-MDIX capabilities, Robust Auto-MDIX will be automatically set to aid in MDI/MDIX resolution and deadlock prevention.

4Fast Auto-Negotiation EnableRW0Fast Auto-Negotiation Enable:
1 = Enable Fast Auto-Negotiation
0 = Disable Fast Auto-Negotiation

The PHY Auto-Negotiaties using timer setting according to Fast Auto-Negotiation Select bits (bits[3:2] in this register).

3:2Fast Auto-Negotiation SelectRW0Fast Auto-Negotiation Select Bits:
Adjusting these bits reduces the time it takes to Auto-Negotiate between two PHYs. In Fast Auto-Negotiation, both PHYs should be set to the same configuration. These 2 bits define the duration for each state of the Auto-Negotiation process according to the table above. The new duration time must be enabled by setting "Fast Auto Negotiation Enable" (bit [4] of this register). Note: Using this mode in cases where both link partners are not configured to the same Fast-Autonegotiation configuration might produce scenarios with unexpected behavior.
Fast Auto-Negotiation SelectBreak Link TimerLink Fail Inhibit TimerAuto-Negotitation Wait Timer
<00>805035
<01>1207550
<10>240150100
<11>NANANA
1Fast RX_DV DetectionRW0Fast RX_DV Detection:
1 = Enable Fast RX_DV detection
0 = Diable Fast RX_DV detection

When Fast RX_DV is enabled, RX_DV will assert high on receive packet due to detection of the /J/ symbol only. If a consecutive /K/ does not appear, RX_ER is generated. In normal mode, RX_DV will only be asserted after detection of /JK/.

0ReservedRO0Reserved
Table 8-24 0x000A Control Register #2 (CR2)
BITNAMETYPEDEFAULTFUNCTION
15100Base-TX Force Far-End Link dropRW0100Base-TX Force Far-End Link Drop:
Writing a 1 asserts the 100Base-TX Force Far-End link drop mode. In this mode (only valid for 100 Mbps), the PHY disables the TX upon link drop to allow the far-end peer to drop its link as well, thus allowing both link partners to be aware of the system link failure. This mode exceeds the standard definition of force 100 Mbps.
14100Base-FX EnableRW, Strap0100Base-FX Enable:
1 = 100Base-FX mode enabled
0 = 100Base-FX mode disabled
13:7ReservedRW00 0001 0Reserved
6Fast Link-Up in Parallel DetectRW0Fast Link-Up in Parallel Detect Mode:
1 = Enable Fast Link-Up time during Paralled Detection
0 = Normal Parallel Detection Link establishment

In Fast Auto MDIX and in Robust Auto-MDIX modes (bit[6] and bit[5] in register CR1), this bit is automatically set.

5Extended Full-Duplex AbilityRW0Extended Full-Duplex Ability:
1 = Enable Extended Full-Duplex Ability
0 = Diable Extended Full-Duplex Ability

In Extended Full-Duplex ability, when the PHY is set to Auto-Negotiation or Force 100Base-TX and the link partner is operated in Force 100Base-TX, the link is always Full-Duplex. When disabled, the decision to work in Full-Duplex or Half-Duplex mode follows IEEE specification.

4Enhanced LED LinkRW0Enhanced LED Link:
1 = LED ON only when link is 100Base-TX Full-Duplex mode
0 = LED ON when link is established

In Enhanced LED Link mode, TX/RX BLINK on activity is disabled for this LED pin. LED will only indicate LINK for established 100Base-TX Full-Duplex links.

3Isolate MII in 100Base-TX Half-Duplex or 10Base-TeRW0Isolate MII:
1 = Isolate MII Enabled
0 = Normal MII output operation

In Isolate MII, MII outputs are isolated when Half-Duplex link established for 100Base-TX or when Half-Duplex or Full-Duplex link established for 10Base-Te.

2RX_ER During IDLERW0Detection of Receive Symbol Error During IDLE State:
1 = Enable detection of Receive symbol error during IDLE state
0 = Disable detection of Receive symbol error during IDLE state
1Odd-Nibble Detection DisableRW0Detection of Transmit Error:
1 = Disable detection of transmit error in odd-nibble boundary
0 = Enable detection of transmit error in odd-nibble boundary

Detection of odd-nibble will extend TX_EN by one additional TX_CLK cycle and behaves as if TX_ER were asserted during that additional cycle

0RMII Receive ClockRW0RMII Receive Clock:
1 = RMII Data (RXD[1:0]) is sampled and referenced to RX_CLK
0 = RMII Data (RXD[1:0]) is sampled and referenced to XI
Table 8-25 0x000B Control Register #3 (CR3)
BITNAMETYPEDEFAULTFUNCTION
15:13ReservedRW000Reserved
12Bypass Digital Equalizer ErrorRW11 = Ignores the intermittent error output of digital equalizer
10De-scrambler Fast Link Down ModeRW0Descrambler Fast Link Drop:
1 = Drop the link on descrambler link loss
0 = Do not drop the link on descrambler link loss

This option can be enabled in parallel to the other fast link down modes in bits[3:0].

9Bypass Digital Equalizer CoefficientRW01 = Bypass 0th coefficient of digital equalizer
8:7ReservedRW00Reserved
6Polarity SwapRW0Polarity Swap:
1 = Inverted polarity on both pairs: TD+ and TD-, RD+ and RD-
0 = Normal polarity

Port Mirror Function:
To enable port mirroring, set this bit and bit [5] high.

5MDI/MDIX SwapRW0MDI/MDIX Swap:
1 = Swap MDI pairs (Receive on TD pair, Transmit on RD pair)
0 = MDI pairs normal (Receive on RD pair, Transmit on TD pair)

Port Mirror Function:
To enable port mirroring, set this bit and bit[6] high.

4ReservedRW0Reserved
3:0Fast Link Down ModeRW0000Fast Link Down Modes:

Bit 3 Drop the link based on RX Error count of the MII interface. When a predefined number of 32 RX Error occurences in a 10μs interval is reached, the link will be dropped.

Bit 2 Drop the link based on MLT3 Error count (Violation of the MLT3 coding in the DSP output). When a predefined number of 20 MLT3 Error occurences in a 10μs interval is reached, the link will be dropped.

Bit 1 Drop the link based on Low SNR Threshold. When a predefined number of 20 Threshold crossing occurences in a 10μs interval is reached, the link will be dropped.

Bit 0 Drop the link based on Signal/Energy Loss indication. When the Energy detector indicates Energy Loss, the link will be dropped. Typical reaction time is 10μs.

The Fast Link Down function is an OR of all 5 options (bit[10] and bits[3:0]), the designer can enable any combination of these conditions.

Table 8-26 0x000D Register Control Register (REGCR)
BITNAMETYPEDEFAULTFUNCTION
15:14Extended Register CommandRW0Extended Register Command:
00 = Address
01 = Data, no post increment
10 = Data, post increment on read and write
11 = Data, post increment on write only
13:5ReservedRO0Reserved
4:0DEVADRW0Device Address:
Bits[4:0] are the device address, DEVAD, that directs any accesses of ADDAR register (0x000E) to the appropriate MMD. Specifically, the DP83822 uses the vendor specific DEVAD [4:0] = "11111" for accesses to registers 0x04D1 and lower. For MMD3 access, the DEVAD[4:0] = '00011'. For MMD7 access, the DEVAD[4:0] = '00111'. All accesses through registers REGCR and ADDAR should use the DEVAD for either MMD, MMD3 or MMD7. Transactions with other DEVAD are ignored.
Table 8-27 0x000E Data Register (ADDAR)
BITNAMETYPEDEFAULTFUNCTION
15:0Address/DataRW0If REGCR register bits[15:14] = '00', holds the MMD DEVAD's address register, otherwise holds the MMD DEVAD's data.
Table 8-28 0x000F Fast Link Down Status Register (FLDS)
BITNAMETYPEDEFAULTFUNCTION
15:9ReservedRO0Reserved
8:4Fast Link Down StatusRO, LH0Fast Link Down Status:
1 0000 = Descrambler Loss Sync
0 1000 = RX Errors
0 0100 = MLT3 Errors
0 0010 = SNR Level
0 0001 = Signal/Energy Lost

Status Registers that latch high each time a given Fast Link Down mode is activated and causes a link drop (assuming the modes were enabled)

3:0ReservedRO0Reserved
Table 8-29 0x0010 PHY Status Register (PHYSTS)
BITNAMETYPEDEFAULTFUNCTION
15ReservedRO0Reserved
14MDI/MDIX ModeRO0MDI/MDIX Mode Status:
1 = MDI Pairs swapped (Receive on TD pair, Transmit on RD pair)
0 = MDI Pairs normal (Receive on RD pair, Transmit on TD pair)
13Receive Error LatchRO, LH0Receive Error Latch:
1 = Receive error event has occurred
0 = No receive error event has occurred

Receive error event has occured since last read of RECR register (address 0x0015). This bit will be cleared upon a read of the RECR register.

12Polarity StatusRO, LH0Polarity Status:
1 = Inverted Polarity detected
0 = Correct Polarity detected

This bit is a duplication of bit[4] in the 10BTSCR register (address 0x001A). This bit will be cleared upon a read of the 10BTSCR register, but not upon a read of the PHYSTS register.

11False Carrier Sense LatchRO, LH0False Carrier Sense Latch:
1 = False Carrier event has occurred
0 = No False Carrier event has occurred

False Carrier event has occurred since last read of FCSCR register (address 0x0014). This bit will be cleared upon a read of the FCSR register.

10Signal DetectRO, LL0Signal Detect:
Active high 100Base-TX unconditional Signal Detect indication from PMD

Note: During EEE_LPI the value of this register bit should be ignored

9Descrambler LockRO, LL0Descrambler Lock:
Active high 100Base-TX Descrambler Lock indication from PMD

Note: During EEE_LPI the value of this register bit should be ignored

8Page ReceivedRO0Link Code Word Page Received:
1 = A new Link Code Word Page has been received
0 = Link Code Word Page has not been received

This bit is a duplicate of Page Received (bit[1]) in the ANER register and it is cleared on read of the ANER register (address 0x0006).

7MII InterruptRO, LH0MII Interrupt Pending:
1 = Indicates that an internal interrupt is pending
0 = No interrupt pending

Interrupt source can be determined by reading the MISR register (0x0012). Reading the MISR will clear this interrupt bit indication.

6Remote FaultRO0Remote Fault:
1 = Remote Fault condition detected
0 = No Remote Fault condition detected

Fault criteria: notification from link partner of Remote Fault via Auto-Negotiation. Cleared on read of BMSR register (address 0x0001) or by reset.

5Jabber DetectRO0Jabber Detection:
1 = Jabber condition detected
0 = No Jabber This bit is only for 10 Mbps operation.

This bit is a duplicate of the Jabber Detect bit in the BMSR register (address 0x0001) and will not be cleared upon a read of the PHYSTS register.

4Auto-Negotiation StatusRO0Auto-Negotiation Status:
1 = Auto-Negotiation complete
0 = Auto-Negotiation not complete
3MII Loopback StatusRO0MII Loopback Status:
1 = Loopback enabled
0 = Normal operation
2Duplex StatusRO0Duplex Status:
1 = Full-Duplex mode
0 = Half-Duplex mode
1Speed StatusRO1Speed Status:
1 = 10 Mbps mode
0 = 100 Mbps mode
0Link StatusRO0Link Status:
1 = Valid link established (for either 10 Mbps or 100 Mbps)
0 = No link established

This bit is duplicated from the Link Status bit in the BMSR register (address 0x0001) and will not be cleared upon a read of the PHYSTS register.

Table 8-30 0x0011 PHY Specific Control Register (PHYSCR)
BITNAMETYPEDEFAULTFUNCTION
15Disable PLLRW0Disable PLL:
1 = Disable internal clocks circuitry
0 = Normal operation

Note: clock circuitry can be disabled only in IEEE power down mode.

14Power Save Mode EnableRW0Power Save Mode Enable:
1 = Enable power save modes
0 = Normal operation
13:12Power Save ModesRW00Power Saving Modes Selection Field:

Power Save Mode Enable (bit[14]) must be set to '1' for power save modes to be enabled.

Power ModeNameDescription
<00>NormalNormal operation mode. PHY is fully functional.
<01>ReservedReserved
<10>Active SleepLow Power Active Energy Saving mode that shuts down all internal circuitry besides SMI and energy detect functionalities. In this mode the PHY sends NLP every 1.4 seconds to wake up link partner. Automatic power-up is done when link partner is detected.
<11>Passive SleepLow Power Passive Energy Saving mode that shuts down all internal circuitry besides SMI and energy detect functionalities. Automatic power-up is done when link partner is detected.
11Scrambler BypassRW0Scrambler Bypass:
1 = Scrambler bypass enabled
0 = Scrambler bypass disabled
10ReservedRW0Reserved
9:8Loopback FIFO DepthRW01Far-End Loopback FIFO Depth:
00 = 4 nibbles FIFO
01 = 5 nibbles FIFO
10 = 6 nibbles FIFO
11 = 8 nibbles FIFO

This FIFO is used to adjust RX (receive) clock rate to TX clock rate. FIFO depth needs to be set based on expected maximum packet size and clock accuracy. Default value sets to 5 nibbles.

7:5ReservedRO0Reserved
4COL Full-Duplex EnableRW0Collision in Full-Duplex Mode:
1 = Enable Collision generation signaling in Full-Duplex mode
0 = Disable Collision in Full-Duplex mode

Note: When in Half-Duplex mode, Collision will always be active.

3Interrupt PolarityRW1Interrupt Polarity:
1 = Normal operation is 1 logic and during interrupt is 0 logic
0 = Normal operation is 0 logic and during interrupt is 1 logic
2Test InterruptRW0Test Interrupt:
1 = Generate an interrupt
0 = Do not generate interrupt

Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts will continue to be generated as long as this bit remains set.

1Interrupt EnableRW0Interrupt Enable:
1 = Enable event based interrupts
0 = Disable event based interrupts

Enable interrupt dependent on the event enables in the MISR register (address 0x0012).

0Interrupt Output EnableRW0Interrupt Output Enable:
1 = INT/PWDN_N is an interrupt output
0 = INT/PWDN_N is a Power Down pin

Enable active low interrupt events via the INT/PWDN_N pin by configuring the INT/PWDN_N pin as an output.

Table 8-31 0x0012 MII Interrupt Status Register #1 (MISR1)
BITNAMETYPEDEFAULTFUNCTION
15Link Quality InterruptRO, LH0Change of Link Quality Status Interrupt:
1 = Change of link quality when link is ON
0 = Link quality is Good
14Energy Detect InterruptRO, LH0Change of Energy Detection Status Interrupt:
1 = Change of energy detected
0 = No change of energy detected
13Link Status Changed InterruptRO, LH0Change of Link Status Interrupt:
1 = Change of link status interrupt is pending
0 = No change of link status
12Speed Changed InterruptRO, LH0Change of Speed Status Interrupt:
1 = Change of speed status interrupt is pending
0 = No change of speed status
11Duplex Mode Changed InterruptRO, LH0Change of Duplex Status Interrupt:
1 = Change of duplex status interrupt is pending
0 = No change of duplex status
10Auto-Negotiation Completed InterruptRO, LH0Auto-Negotiation Complete Interrupt:
1 = Auto-Negotiation complete interrupt is pending
0 = No Auto-Negotiation complete event is pending
9False Carrier Counter Half-Full InterruptRO, LH0False Carrier Counter Half-Full Interrupt:
1 = False Carrier HF interrupt is pending
0 = False Carrier HF event is not pending

False Carrier counter (Register FCSCR, address 0x0014) exceeds half-full interrupt is pending.

8Receive Error Counter Half-Full InterruptRO, LH0Receiver Error Counter Half-Full Interrupt:
1 = Receive Error HF interrupt is pending
0 = Receive Error HF event is not pending

Receiver Error counter (Register RECR, address 0x0015) exceeds half-full interrupt is pending.

7Link Quality Interrupt EnableRW0Enable interrupt on change of link quality
6Energy Detect Interrupt EnableRW0Enable interrupt on change of energy detection
5Link Status Changed EnableRW0Enable interrupt on change of link status
4Speed Changed Interrupt EnableRW0Enable Interrupt on change of speed status
3Duplex Mode Changed Interrupt EnableRW0Enable Interrupt on change of duplex status
2Auto-Negotiation Completed EnableRW0Enable Interrupt on Auto-negotiation complete event
1False Carrier HF EnableRW0Enable Interrupt on False Carrier Counter Register half-full event
0Receive Error HF EnableRW0Enable Interrupt on Receive Error Counter Register half-full event
Table 8-32 0x0013 MII Interrupt Status Register #2 (MISR2)
BITNAMETYPEDEFAULTFUNCTION
15EEE Error InterruptRO, LH0Energy Efficient Ethernet Error Interrupt:
1 = EEE error has occurred
0 = EEE error has not occurred
14Auto-Negotiation Error InterruptRO, LH0Auto-Negotiation Error Interrupt:
1 = Auto-Negotiation error interrupt is pending
0 = No Auto-Negotiation error event pending
13Page Received InterruptRO, LH0Page Receiver Interrupt:
1 = Page has been received
0 = Page has not been received
12Loopback FIFO OF/UF Event InterruptRO, LH0Loopback FIFO Overflow/Underflow Event Interrupt:
1 = FIFO Overflow/Underflow event interrupt pending
0 = No FIFO Overflow/Underflow event pending
11MDI Crossover Change InterruptRO, LH0MDI/MDIX Crossover Status Change Interrupt:
1 = MDI crossover status changed interrupt is pending
0 = MDI crossover status has not changed
10Sleep Mode InterruptRO, LH0Sleep Mode Event Interrupt:
1 = Sleep mode event interrupt is pending
0 = No Sleep mode event pending
9Polarity Changed Interrupt / WoL Packet Received InterruptRO, LH0Polarity Change Interrupt / WoL Packet Received Interrupt:
1 = Data polarity interrupt pending / WoL packet was recieved
0 = No Data polarity pending / No WoL packet received
8Jabber Detect InterruptRO, LH0Jabber Detect Event Interrupt:
1 = Jabber detect event interrupt pending
0 = No Jabber detect event pending
7EEE Error Interrupt EnableRW0Enable interrupt on EEE Error
6Auto-Negotiation Error Interrupt EnableRW0Enable Interrupt on Auto-Negotiation error event
5Page Received Interrupt EnableRW0Enable Interrupt on page receive event
4Loopback FIFO OF/UF EnableRW0Enable Interrupt on loopback FIFO Overflow/Underflow event
3MDI Crossover Change EnableRW0Enable Interrupt on change of MDI/X status
2Sleep Mode Event EnableRW0Enable Interrupt on sleep mode event
1Polarity Changed / WoL Packet EnableRW0Enable Interrupt on change of polarity status
0Jabber Detect EnableRW0Enable Interrupt on Jabber detection event
Table 8-33 0x0014 False Carrier Sense Counter Register (FCSCR)
BITNAMETYPEDEFAULTFUNCTION
15:8ReservedRO0Reserved
7:0False Carrier Event CounterRO, COR0False Carrier Event Counter:
This 8-bit counter increments on every false carrier event. This counter stops when it reaches its maximum count (FFh). When the counter exceeds half-full (7Fh), an interrupt event is generated. This register is cleared on read.
Table 8-34 0x0015 Receive Error Count Register (RECR)
BITNAMETYPEDEFAULTFUNCTION
15:0Receive Error CounterRO, COR0RX_ER Counter:
When a valid carrier is presented (only while RXDV is set), and there is at least one occurrence of an invalid data symbol, this 16-bit counter increments for each receive error detected. The RX_ER counter does not count in MII loopback mode. The counter stops when it reaches its maximum count (FFFFh). When the counter exceeds half-full (7Fh), an interrupt is generated. This register is cleared on read.
Table 8-35 0x0016 BIST Control Register (BISCR)
BITNAMETYPEDEFAULTFUNCTION
15ReservedRO0Reserved
14BIST Error Counter ModeRW0BIST Error Counter Mode:
1 = Continuous mode
0 = Single mode

Continuous mode, when the BIST Error counter reaches its max value, a pulse is generated and the counter starts counting from zero again. When in Single mode, if the BIST Error Counter reaches its max value, PRBS checker will stop counting.

13PRBS CheckerRW0PRBS Checker:
1 = PRBS Checker Enabled
0 = PRBS Checker Disabled

When PRBS checker is enabled, DP83822 will check PRBS data received.

12Packet Generation EnableRW0Packet Generation Enable:
1 = Enable packet generator with PRBS data
0 = Disable packet generator
11PRBS Checker Lock/SyncRO0PRBS Checker Lock/Sync Indication:
1 = PRBS checker is locked and synced on received bit stream
0 = PRBS checker is not locked
10PRBS Checker Sync LossRO, LH0PRBS Checker Sync Loss Indication:
1 = PRBS checker has lost sync
0 = PRBS checker has not lost sync
9Packet Generator StatusRO0Packet Generation Status Indication:
1 = Packet Generator is active and generating packets
0 = Packet Generator is off
8Power ModeRO1Sleep Mode Indication:
1 = Indicates that the PHY is in normal power mode
0 = Indicates that the PHY is in one of the sleep modes
7ReservedRO0Reserved
6Transmit in MII LoopbackRW0Transmit Data in MII Loopback Mode (valid only at 100 Mbps):
1 = Enable transmission
0 = Disable transmission

When enabled, data received from the MAC on the TX pins will be routed to the MDI in parallel to the MII loopback (to RX pins). This bit may be set only in MII Loopback mode - setting bit[14] in in BMCR register (address 0x0000). When disabled, data from the MAC is not transmitted to the MDI.

5ReservedRO0Reserved
4:0Loopback ModeRW0Loopback Mode Select:
The PHY provides several options for loopback that test and verify various functional blocks within the PHY. Enabling loopback mode allows in-circuit testing of the DP83822 digital and analog data paths Near-end Loopback
00001 = PCS Input Loopback
00010 = PCS Output Loopback
00100 = Digital Loopback
01000 = Analog Loopback (requires 100-Ω termination) Far-end Loopback
10000 = Reverse Loopback
Table 8-36 0x0017 RMII and Status Register (RCSR)
BITNAMETYPEDEFAULTFUNCTION
15:13ReservedRO0Reserved
12RGMII RX Clock ShiftRW0RGMII RX Clock Shift:
1 = Receive path internal clock shift is enabled
0 = Receive path internal clock shift is disabled

When enabled, receive path internal clock (RX_CLK) is delayed by 3.5ns relative to recieve data. When disabled, data and clock are in align mode.

11RGMII TX Clock ShiftRW0RGMII TX Clock Shift:
1 = Transmit path internal clock shift is disabled
0 = Transmit path internal clock shift is enabled

When enabled, transmit path internal clock (TX_CLK) is delayed by 3.5ns relative to transmit data.

10RGMII TX SyncedRW0RGMII TX Clock Sync:
1 = PHY and MAC share same clock reference
0 = PHY operates from same or independent clock source as MAC

This mode, when enabled, reduces latency since both MAC and PHY are synchronized to the same clock source. This mode can also be used when enabling the PHY Clock Output by connecting the MAC to the PHY Output Clock.

9RGMII ModeRW, Strap0RGMII Mode Enable:
1 = Enable RGMII mode of operation
0 = Mode determined by bit[5]
8RMII TX Clock ShiftRW0RMII TX Clock Shift:

1 = Transmit path internal clock shift is enabled
0 = Transmit path internal clock shift is disabled
7RMII Clock SelectRW, Strap0RMII Reference Clock Select:
Strap XI_50 determines the clock reference requirement.
1 = 50-MHz clock reference, CMOS-level oscillator
0 = 25-MHz clock reference, crystal or CMOS-level oscillator
6RMII Recovered Clock Async FIFO BypassRW1RMII Recovered Clock Async FIFO Bypass:
0 = Bypass Asynchronous FIFO
1 = Normal operation

When in RMII Recovered Clock mode, the asynchronous FIFO can be bypassed to reduce the receive path latency within the DP83822.


50-MHz clock is outputted on RX_CLK when in Async fifo bypass
5RMII ModeRW0RMII Mode Enable:
1 = Enable RMII mode of operation
0 = Enable MII mode of operation
4RMII Revision SelectRW0RMII Revision Select:
1 = RMII revision 1.0
0 = RMII revision 1.2

RMII revision 1.0, CRS_DV will remain asserted until final data is transferred. CRS_DV will not toggle at the end of a packet.

RMII revision 1.2, CRS_DV will toggle at the end of a packet to indicate de-assertion of CRS.

3RMII Overflow StatusRO, COR0RX FIFO Overflow Status:
1 = Overflow detected
0 = Normal
2RMII Underflow StatusRO, COR0RX FIFO Underflow Status:
1 = Underflow detected
0 = Normal
1:0Receive Elasticity Buffer SizeRW01Receive Elasticity Buffer Size:
This field controls the Receive Elasticity Buffer which allows for frequency variation tolerance between the 50-MHz RMII clock and the recovered data. The following values indicate the tolerance in bits for a single packet. The minimum setting allows for standard Ethernet frame sizes at ±50ppm accuracy. For greater frequency tolerance, the packet lengths may be scaled (for ±100ppm), divide the packet lengths by 2). 00 = 14 bit tolerance (up to 16800 byte packets)
01 = 2 bit tolerance (up to 2400 byte packets)
10 = 6 bit tolerance (up to 7200 byte packets)
11 = 10 bit tolerance (up to 12000 byte packets)
Table 8-37 0x0018 LED Control Register (LEDCR)
BITNAMETYPEDEFAULTFUNCTION
15:11ReservedRO0Reserved
10:9Blink RateRW10LED_0 Blinking Rate (ON/OFF duration):
00 = 20Hz (50 ms)
01 = 10Hz (100 ms)
10 = 5Hz (200 ms)
11 = 2Hz (500 ms)
8ReservedRW0Reserved
7LED_0 PolarityRW, Strap0LED_0 Link Polarity Setting:
1 = Active High polarity setting
0 = Active Low polarity setting

LED_0 polarity defined by strapping value of this pin. This register allows for override of this strap value.

6:5ReservedRW0Reserved
4Drive LED_0RW0Drive Link LED_0 Select:
1 = Drive value of ON/OFF bit[1] onto LED_0 output pin
0 = Normal operation
3:2ReservedRW0Reserved
1LED_0 ON/OFF SettingRW0Value to force LED_0 output
0ReservedRW0Reserved
Table 8-38 0x0019 PHY Control Register (PHYCR)
BITNAMETYPEDEFAULTFUNCTION
15Auto MDI/X EnableRW, Strap0Auto-MDIX Enable:
1 = Enable Auto-Negotiation Auto-MDIX capability
0 = Disable Auto-Negotiation Auto-MDIX capability
14Force MDI/XRW0Force MDIX:
1 = Force MDI pairs to cross (MDIX)
0 = Normal operation (MDI)

When Force MDI/X is enabled, receive data is on the TD pair and transmit data is on the RD pair. When disabled, receive data is on the RD pair and transmit data is on the TD pair.

13Pause RX StatusRO0Pause Receive Negotiation Status:
Indicates that pause receive should be enabled in the MAC. Based on bits[11:10] in ANAR register and bits[11:10] in ANLPAR register settings. The function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, "Pause Resolution", only if the Auto-Negotiation highest common denominator is a Full-Duplex technology.
12Pause TX StatusRO0Pause Transmit Negotiated Status:
Indicates that pause should be enabled in the MAC. Based on bits[11:10] in ANAR register and bits[11:10] in ANLPAR register settings. This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, "Pause Resolution", only if the Auto-Negotiation highest common denominator is a Full-Duplex technology.
11MII Link StatusRO0MII Link Status:
1 = 100Base-TX Full-Duplex link is active
0 = No active 100Base-TX Full-Duplex link
10:8ReservedRO0Reserved
7Bypass LED StretchingRW0Bypass LED Stretching:
1 = Bypass LED stretching
0 = Normal LED operation

Set this bit to '1' to bypass the LED stretching, the LED reflects the internal value.

6ReservedRW0Reserved
5LED ConfigurationRW, Strap1ConfigurationLED_CFGLED_0
11ON for LINK
OFF for no LINK
20ON for LINK
BLINK for TX/RX Activity
4:0PHY AddressRO, Strap0000 1PHY Address:
Strapping configuration for PHY Address
Table 8-39 0x001A 10Base-Te Status/Control Register (10BTSCR)
BITNAMETYPEDEFAULTFUNCTION
15:14ReservedRO0Reserved
13Receiver Threshold EnableRW0Lower Receiver Threshold Enable:
1 = Enable 10Base-Te lower receiver threshold
0 = Normal 10Base-Te operation

When enabled, receiver threshold is lowered to allow for operation with longer cables.

12:9SquelchRW0000Squelch Configuration: Used to set the Peak Squelch 'ON' threshold for the 10Base-Te receiver. Starting from 200mV to 600mV, step size of 50mV with some overlapping as shown below: 0000 = 200mV
0001 = 250mV
0010 = 300mV
0011 = 350mV
0100 = 400mV
0101 = 450mV
0110 = 500mV
0111 = 550mV
1000 = 600mV
8ReservedRW0Reserved
7NLP DisableRW0NLP Transmission Control:
1 = Disable transmission of NLPs
0 = Enable transmission of NLPs
6:5ReservedRO0Reserved
4Polarity StatusRO0Polarity Status:
1 = Inverted Polarity detected
0 = Correct Polarity detected

This bit is a duplication of bit[12] in the PHYSTS register (0x0010). Both bits will be cleared upon a read of 10BTSCR register, but not upon a read of the PHYSTS register.

3:1ReservedRO0Reserved
0Jabber DisableRW0Jabber Disable:
1 = Jabber function disabled
0 = Jabber function enabled

Note: This function is only applicable in 10Base-Te operation.

Table 8-40 0x001B BIST Control and Status Register #1 (BICSR1)
BITNAMETYPEDEFAULTFUNCTION
15:8BIST Error CountRO0x0BIST Error Count:
Holds number of errored bytes received by the PRBS checker. Value in this register is locked and cleared when write is done to bit[15]. When BIST Error Counter Mode is set to '0', count stops on 0xFF (see register 0x0016)

Note: Writing '1' to bit[15] will lock the counter's value for successive read operation and clear the BIST Error Counter.

7:0BIST IPG LengthRW0111 1101BIST IPG Length:
Inter Packet Gap (IPG) Length defines the size of the gap (in bytes) between any 2 successive packets generated by the BIST. Default value is 0x7D (equal to 500 bytes).
Table 8-41 0x001C BIST Control and Status Register #2 (BICSR2)
BITNAMETYPEDEFAULTFUNCTION
15:11ReservedRO0Reserved
10:0BIST Packet LengthRW101 1110 1110BIST Packet Length:
Length of the generated BIST packets. The value of this register defines the size (in bytes) of every packet that is generated by the BIST. Default value is 0x5EE, which is equal to 1518 bytes.
Table 8-42 0x001E Cable Diagnostic Control Register (CDCR)
BITNAMETYPEDEFAULTFUNCTION
15Cable Diagnostic StartRW0Cable Diagnostic Process Start:
1 = Start cable measurement
0 = Cable Diagnostic is disabled

Diagnostic Start bit is cleared once Diagnostic Done indication bit is triggered.

14:2ReservedRO000 0001 0000 00Reserved
1Cable Diagnostic StatusRO1Cable Diagnostic Process Done:
1 = Indication that cable measurement process is complete
0 = Cable Diagnostic had not completed
0Cable Diagnostic Test FailRO0Cable Diagnostic Process Fail:
1 = Indication that cable measurement process failed
0 = Cable Diagnostic has not failed
Table 8-43 0x001F PHY Reset Control Register (PHYRCR)
BITNAMETYPEDEFAULTFUNCTION
15Software ResetRW, SC0Software Reset:
1 = Reset PHY
0 = Normal Operation

This bit is self cleared and has the same effect as Hardware reset pin.

14Digital RestartRW, SC0Digital Restart:
1 = Restart PHY
0 = Normal Operation

This bit is self cleared and resets all PHY digital circuitry except the registers.

13:0ReservedRW0Reserved
Table 8-44 0x0025 Multi-LED Control Register (MLEDCR)
BITNAMETYPEDEFAULTFUNCTION
15:10ReservedRW0Reserved
9MLED Polarity SwapRWStrapMLED Polarity Swap:
The polarity of MLED depends on the routing configuration. If the pin strap is Pull-Up then polarity is active low. If the pin strap is Pull-Down then polarity is active high.
0 = Active Low (default when pin strapped HIGH)
1 = Active High (default when pin strapped LOW)
8:7ReservedRW0Reserved
6:3MLED ConfigurationRW000 0MLED Configurations:
000 0 = LINK OK
000 1 = RX/TX Activity
001 0 = TX Activity
001 1 = RX Activity
010 0 = Collision
010 1 = Speed, High for 100Base-TX
011 0 = Speed, High for 10Base-Te
011 1 = Full-Duplex
100 0 = LINK OK / BLINK on TX/RX Activity
100 1 = Active Stretch Signal
101 0 = MII LINK (100BT+FD)
101 1 = LPI Mode (EEE)
110 0 = TX/RX MII Error
110 1 = Link Lost
111 0 = Blink for PRBS error
111 1 = Reserved

Link Lost, LED remains ON until BMCR register (address 0x0001) is read.

Blink for PRBS Errors, LED remains ON for single error and remains until BICSR1 register (address 0x001B) is cleared.

2ReservedRW0Reserved
1:0MLED Route to LED_0RW00MLED Route to LED_0:
00 = MLED routed to COL
01 = Reserved
10 = Reserved
11 = MLED routed to LED_0
Table 8-45 0x0027 Compliance Test Register (COMPT)
BITNAMETYPEDEFAULTFUNCTION
15:5ReservedRW0Reserved
410Base-Te Test Patterns EnableRW010Base-Te Test Pattern Enable:
1 = Enable 10Base-Te Test Patterns
0 = Disable 10Base-Te Test Patterns
3:0Compliance Test ConfigurationRW0000Compliance Test Configuration Select:

Bit[4] in Register 0x0027 = 1, Enables 10Base-Te Test Patterns.

Bit[4] in Register 0x0428 = 1, Enables 100Base-TX Test Modes

Bits[3:0] select the 10Base-Te test pattern, as follows:


0000 = Single NLP
0001 = Single Pulse 1
0010 = Single Pulse 0
0011 = Repetitive 1
0100 = Repetitive 0
0101 = Preamble (repetitive ‘10’)
0110 = Single 1 followed by TP_IDLE
0111 = Single 0 followed by TP_IDLE
1000 = Repetitive ‘1001’ sequence
1001 = Random 10Base-Te data
1010 = TP_IDLE_00
1011 = TP_IDLE_01
1100 = TP_IDLE_10
1101 = TP_IDLE_11

100Base-TX Test Mode is determined by bits \{[5] in register 0x0428, [3:0] in register 0x0027\}. The bits determine the number of 0's to follow a '1'.


0,0001 = Single '0' after a '1'
0,0010 = Two '0' after a '1'
0,0011 = Three '0' after a '1'
0,0100 = Four '0' after a '1'
0,0101 = Five '0' after a '1'
0,0110 = Six '0' after a '1'
0,0111 = Seven '0' after a '1'
...
1,1111 = Thirty one '0' after a '1'
0,0000 = Clears the shift register

Note 1: To reconfigure the 100Base-TX Test Mode, bit[4] must be cleared in register 0x0428 and then reset to '1' to configure the new pattern.

Note 2: When performing 100Base-TX or 10Base-Te tests modes, the speed must be forced using the Basic Mode Control Register (BMCR), address 0x0000.

Table 8-46 0x003E IEEE 1588 PTP Pin Select Register (PTPPSEL)
BITNAMETYPEDEFAULTFUNCTION
15:7ReservedRO0Reserved
6:4IEEE 1588 TX Pin SelectRW000IEEE 1588 TX Pin Select:
Assigns transmit SFD pulse indication to pin selected by value

001 = Reserved
010 = Reserved
011 = LED_0 Pin
100 = CRS Pin
101 = COL Pin
110 = INT/PWDN_N Pin
111 = No pulse output
3ReservedRO0Reserved
2:0IEEE 1588 RX Pin SelectRW000IEEE 1588 RX Pin Select:
Assigns receive SFD pulse indication to pin selected by value

001 = Reserved
010 = Reserved
011 = LED_0 Pin
100 = CRS Pin
101 = COL Pin
110 = INT/PWDN_N Pin
111 = No pulse output
Table 8-47 0x003F IEEE 1588 PTP Configuration Register IEEE 1588 Precision Timing Configuration Register (PTPCFG)
BITNAMETYPEDEFAULTFUNCTION
15:13PTP Transmit TimingRW101PTP Transmit Timing:
Set IEEE 1588 indication for TX path (8ns step)
12:10PTP Receive TimingRW101PTP Receive Timing:
Set IEEE 1588 indication for RX path (8ns step)
9:8TX Error Input PinRW00Configure TX Error Input Pin:
00 = No TX Error
01 = Reserved
10 = Use INT/PWDN_N pin as TX error
11 = Use COL pin as TX error
7:4Timer For De-scrambler Unlock Based Link-DownRW1111
3:0ReservedRW1111Reserved
Table 8-48 0x0040 Fiber Far-End Fault Generation/Detection Force
BITNAMETYPEDEFAULTFUNCTION
15:7ReservedRW1100 0001 0Reserved
6FEF Gen DisableRW01=Far end fault generation is disabled
5FEF Detect DisableRW01=Disable detection of far end fault
4:0ReservedRW1 1101Reserved
Table 8-49 0x0042 TX_CLK Phase Shift Register (TXCPSR)
BITNAMETYPEDEFAULTFUNCTION
15:5ReservedRO0Reserved
4Phase Shift EnableRW, SC0TX Clock Phase Shift Enable:
1 = Perform Phase Shift to TX_CLK
0 = No change in TX_CLK phase

When enabled, TX_CLK phase shift is according to the value written to TX Clock Phase Shift Value (bits[4:0]).

3:0Phase Shift ValueRW0000TX Clock Phase Shift Value:
The value of this register represents the current phase shift between Reference clock at XI and MII tramsmit clock at TX_CLK. Any different value that will be written to these bits will shift TX_CLK by 4 times the difference (in ns).

Example: If the value of the register is 0x0002, writing 0x0009 to this register will shift TX_CLK by 28ns. (4 times 7ns)

Table 8-50 0x0101 DSP Configuration Register 1 (DSPCR1)
BITNAMETYPEDEFAULTFUNCTION
15:8ReservedRW0010 0000Reserved
7Internal Filter DisableRW01 = Disable internal filter during a phase of link-up training
Table 8-51 0x0106 Digital Filter Configuration Register 1 (DFCR1)
BITNAMETYPEDEFAULTFUNCTION
15:12Internal Threshold For FilterRW1011Internal threshold to activate filter coefficients set1 for short cables.
11Reserved0Reserved
10Enable Filter CoefficientRW01= Enable internal filter coefficient in steady state
9:8ReservedRW00Reserved
7:6Filter CoefficientsRW10Filter coefficient values for long cables
5:4ReservedRW11Reserved
3:0Internal Threshold For FilterRW1011Internal threshold to activate filter coefficients set0 for short cables.
Table 8-52 0x0107 Digital Filter Configuration Register 2 (DFCR2)
BITNAMETYPEDEFAULTFUNCTION
15:0ReservedRW0000 0110 0000 0101Reserved
Table 8-53 0x010F DSP Configuration Register 2 (DSPCR2)
BITNAMETYPEDEFAULTFUNCTION
15:9ReservedRW0000 001Reserved
8DSP Loop InputRW1Selects the type of input for the gain correction loop
7:0ReservedRW0000 0000Reserved
Table 8-54 0x0111 DSP Configuration Register 3 (DSPCR3)
BITNAMETYPEDEFAULTFUNCTION
15:4ReservedRW0110 0000 0000Reserved
3:0Starting Gain IndexRW011Initial value of gain index
Table 8-55 0x0114 Digital Feedback Equalizer Control Register (DFECR)
BITNAMETYPEDEFAULTFUNCTION
15:0ReservedRW0100 0000 0000 1010Reserved
Table 8-56 0x0116 AGC Bandwidth Control Register (AGCBCR)
BITNAMETYPEDEFAULTFUNCTION
15:0ReservedRW0000 0001 0100 1010Reserved
Table 8-57 0x0121 MSE Threshold To Enter Recovery State From Steady State
BITNAMETYPEDEFAULTFUNCTION
15ReservedRO0Ignore on read
14:0Bad MSE ThresholdRW001 1001 1001 1010Bad MSE threshold for 100M
Table 8-58 0x0122 MSE Threshold For Timing Loop
BITNAMETYPEDEFAULTFUNCTION
15ReservedRO0Ignore on read
14:0Good MSE1 ThresholdRW001 0000 0010 0111Good MSE1 threshold for 100M
Table 8-59 0x0123 MSE Threshold For Link-up
BITNAMETYPEDEFAULTFUNCTION
15ReservedRO0Ignore on read
14:0Good MSE2 ThresholdRW000 0101 0001 1100Good MSE2 threshold for 100M
Table 8-60 0x0126 Digital Equalizer Timer Register (DETR)
BITNAMETYPEDEFAULTFUNCTION
15ReservedRW0Reserved
14:12Training Timer 1RW100Timer value used for DSP state shift
11:6Training Timer 2RW0110 00Timer value used in timing loop
5:3Training Timer 3RW011Timer value used in gain loop
2:0Training Timer 4RW011Timer value used in gain loop
Table 8-61 0x0129 DSP Configuration Register 4 (DSPCR4)
BITNAMETYPEDEFAULTFUNCTION
15:8ReservedRW0000 0000Reserved
7:4Max Gain IndexRW0000Limit of max gain index
3:0Min Gain IndexRW1111Limit of min gain index
Table 8-62 0x0130 DSP Configuration Register 5 (DSPCR5)
BITNAMETYPEDEFAULTFUNCTION
15:12ReservedRW0000Reserved
11Disable Gain RetrainRW01 = Disable Gain Retraining
10:0ReservedRW000 0000 0001Reserved
Table 8-63 0x0155 ALCD Control and Results 1 Register (ALCDRR1)
BITNAMETYPEDEFAULTFUNCTION
15ALCD Start TestSC0Active Link Cable Diagnostic Start:
1 = Start ALCD test
0 = Do not start ALCD test
14:13ReservedRO00Reserved
12ALCD Test StatusRO0Active Link Cable Diagnostic Status:
1 = ALCD is not complete
0 = ALCD is complete
11:4ALCD Sum OutRO0000 0000
3:0ReservedRW0001Reserved
Table 8-64 0x0170 Cable Diagnostic Specific Control Register (CDSCR)
BITNAMETYPEDEFAULTFUNCTION
15ReservedRO0Reserved
14Cable Diagnostic Cross DisableRW0Cross TDR Diagnostic Mode:
1 = Disable TDR Cross Mode
0 = Enable TDR Cross Mode

When enabled, the TDR mechanism is looking for reflection on the other pair to check for shorts between pairs.

13Cable Diagnostic TD BypassRW0TD Diagnostic Bypass:
1 = Bypass TD pair diagnostic
0 = TDR is executed on TD pair

When enabled, TDR on TD pair will not be executed.

12Cable Diagnostic RD BypassRW0RD Diganostic Bypass:
1= Bypass RD pair diagnostic
0 = TDR is executed on RD pair

When enabled, TDR on RD pair will not be executed.

11ReservedRW1Reserved
10:8Cable Diagnostic Average CyclesRW110Number of TDR Cycles to Average:
000 = 1 TDR cycle
001 = 2 TDR cycles
010 = 4 TDR cycles
011 = 8 TDR cycles
100 = 16 TDR cycles
101 = 32 TDR cycles
110 = 64 TDR cycles
111 = Reserved
7:0ReservedRW0101 0010Reserved
Table 8-65 0x0171 Cable Diagnostic Specific Control Register 2 (CDSCR2)
BITNAMETYPEDEFAULTFUNCTION
15:4ReservedRW1100 1000 0101Reserved
3:0TDR Pulse ControlRW1100Configure expected self reflection in TDR
Table 8-66 0x0173 Cable Diagnostic Specific Control Register 3 (CDSCR3)
BITNAMETYPEDEFAULTFUNCTION
15:8Cable Length ConfigurationRW1111 1111Configure duration of listening to detect long cable reflections
7:0ReservedRW0001 1110Reserved
Table 8-67 0x0177 Cable Diagnostic Specific Control Register 4 (CDSCR4)
BITNAMETYPEDEFAULTFUNCTION
15:13ReservedRW000Reserved
12:8Short Cables ThresholdRW1 1000Threshold to compensate for strong reflections in short cables
7:0ReservedRW1001 1011Reserved
Table 8-68 0x0180 Cable Diagnostic Location Result Register #1 (CDLRR1)
BITNAMETYPEDEFAULTFUNCTION
15:8TD Peak Location 2RO0000 0000Location of the Second peak discovered by the TDR mechanism on Transmit Channel (TD). The value of these bits need to be translated into distance from the PHY.
7:0TD Peak Location 1RO0000 0000Location of the First peak discovered by the TDR mechanism on Transmit Channel (TD). The value of these bits need to be translated into distance from the PHY.
Table 8-69 0x0181 Cable Diagnostic Location Result Register #2 (CDLRR2)
BITNAMETYPEDEFAULTFUNCTION
15:8TD Peak Location 4RO0000 0000Location of the Fourth peak discovered by the TDR mechanism on Transmit Channel (TD). The value of these bits need to be translated into distance from the PHY.
7:0TD Peak Location 3RO0000 0000Location of the Third peak discovered by the TDR mechanism on Transmit Channel (TD). The value of these bits need to be translated into distance from the PHY.
Table 8-70 0x0182 Cable Diagnostic Location Result Register #3 (CDLRR3)
BITNAMETYPEDEFAULTFUNCTION
15:8RD Peak Location 1RO0000 0000Location of the First peak discovered by the TDR mechanism on Receive Channel (RD). The value of these bits need to be translated into distance from the PHY.
7:0TD Peak Location 5RO0000 0000Location of the Fifth peak discovered by the TDR mechanism on Transmit Channel (TD). The value of these bits need to be translated into distance from the PHY.
Table 8-71 0x0183 Cable Diagnostic Location Result Register #4 (CDLRR4)
BITNAMETYPEDEFAULTFUNCTION
15:8RD Peak Location 3RO0000 0000Location of the Third peak discovered by the TDR mechanism on Receive Channel (RD). The value of these bits need to be translated into distance from the PHY.
7:0RD Peak Location 2RO0000 0000Location of the Second peak discovered by the TDR mechanism on Receive Channel (RD). The value of these bits need to be translated into distance from the PHY.
Table 8-72 0x0184 Cable Diagnostic Location Result Register #5 (CDLRR5)
BITNAMETYPEDEFAULTFUNCTION
15:8RD Peak Location 5RO0000 0000Location of the Fifth peak discovered by the TDR mechanism on Receive Channel (RD). The value of these bits need to be translated into distance from the PHY.
7:0RD Peak Location 4RO0000 0000Location of the Fourth peak discovered by the TDR mechanism on Receive Channel (RD). The value of these bits need to be translated into distance from the PHY.
Table 8-73 0x0185 Cable Diagnostic Amplitude Result Register #1 (CDLAR1)
BITNAMETYPEDEFAULTFUNCTION
15ReservedRO0Reserved
14:8TD Peak Amplitude 2RO000 0000Amplitude of the Second peak discovered by the TDR mechanism on Transmit Channel (TD). The value of these bits is translated into type of cable fault and/or interference.
7ReservedRO0Reserved
6:0TD Peak Amplitude 1RO000 0000Amplitude of the First peak discovered by the TDR mechanism on Transmit Channel (TD). The value of these bits is translated into type of cable fault and/or interference.
Table 8-74 0x0186 Cable Diagnostic Amplitude Result Register #2 (CDLAR2)
BITNAMETYPEDEFAULTFUNCTION
15ReservedRO0Reserved
14:8TD Peak Amplitude 4RO000 0000Amplitude of the Fourth peak discovered by the TDR mechanism on Transmit Channel (TD). The value of these bits is translated into type of cable fault and/or interference.
7ReservedRO0Reserved
6:0TD Peak Amplitude 3RO000 0000Amplitude of the Third peak discovered by the TDR mechanism on Transmit Channel (TD). The value of these bits is translated into type of cable fault and/or interference.
Table 8-75 0x0187 Cable Diagnostic Amplitude Result Register #3 (CDLAR3)
BITNAMETYPEDEFAULTFUNCTION
15ReservedRO0Reserved
14:8RD Peak Amplitude 1RO000 0000Amplitude of the First peak discovered by the TDR mechanism on Receive Channel (RD). The value of these bits is translated into type of cable fault and/or interference.
7ReservedRO0Reserved
6:0TD Peak Amplitude 5RO000 0000Amplitude of the Fifth peak discovered by the TDR mechanism on Transmit Channel (TD). The value of these bits is translated into type of cable fault and/or interference.
Table 8-76 0x0188 Cable Diagnostic Amplitude Result Register #4 (CDLAR4)
BITNAMETYPEDEFAULTFUNCTION
15ReservedRO0Reserved
14:8RD Peak Amplitude 3RO000 0000Amplitude of the Third peak discovered by the TDR mechanism on Receive Channel (RD). The value of these bits is translated into type of cable fault and/or interference.
7ReservedRO0Reserved
6:0RD Peak Amplitude 2RO000 0000Amplitude of the Second peak discovered by the TDR mechanism on Receive Channel (RD). The value of these bits is translated into type of cable fault and/or interference.
Table 8-77 0x0189 Cable Diagnostic Amplitude Result Register #5 (CDLAR5)
BITNAMETYPEDEFAULTFUNCTION
15ReservedRO0Reserved
14:8RD Peak Amplitude 5RO000 0000Amplitude of the Fifth peak discovered by the TDR mechanism on Receive Channel (RD). The value of these bits is translated into type of cable fault and/or interference.
7ReservedRO0Reserved
6:0RD Peak Amplitude 4RO000 0000Amplitude of the Fourth peak discovered by the TDR mechanism on Receive Channel (RD). The value of these bits is translated into type of cable fault and/or interference.
Table 8-78 0x018A Cable Diagnostic General Result Register (CDLGR)
BITNAMETYPEDEFAULTFUNCTION
15TD Peak Polarity 5RO0Polarity of the Fifth peak discovered by the TDR mechanism on Transmit Channel (TD).
14TD Peak Polarity 4RO0Polarity of the Fourth peak discovered by the TDR mechanism on Transmit Channel (TD).
13TD Peak Polarity 3RO0Polarity of the Third peak discovered by the TDR mechanism on Transmit Channel (TD).
12TD Peak Polarity 2RO0Polarity of the Second peak discovered by the TDR mechanism on Transmit Channel (TD).
11TD Peak Polarity 1RO0Polarity of the First peak discovered by the TDR mechanism on Transmit Channel (TD).
10RD Peak Polarity 5RO0Polarity of the Fifth peak discovered by the TDR mechanism on Receive Channel (RD).
9RD Peak Polarity 4RO0Polarity of the Fourth peak discovered by the TDR mechanism on Receive Channel (RD).
8RD Peak Polarity 3RO0Polarity of the Third peak discovered by the TDR mechanism on Receive Channel (RD).
7RD Peak Polarity 2RO0Polarity of the Second peak discovered by the TDR mechanism on Receive Channel (RD).
6RD Peak Polarity 1RO0Polarity of the First peak discovered by the TDR mechanism on Receive Channel (RD).
5Cross Detect on TDRO0Cross Reflections were detected on TD. Indicate on Short between TD and TD
4Cross Detect on RDRO0Cross Reflections were detected on RD. Indicate on Short between TD and RD
3Above 5 TD PeaksRO0More than 5 reflections were detected on TD
2Above 5 RD PeaksRO0More than 5 reflections were detected on RD
1:0ReservedRO0Reserved
Table 8-79 0x0215 ALCD Control and Results 2 Register (ALCDRR2)
BITNAMETYPEDEFAULTFUNCTION
15:4ReservedRO0000 0000 0000Reserved
3:0PGA ControlRO1111Control word to analog PGA
Table 8-80 0x021D ALCD Control and Results 3 Register (ALCDRR3)
BITNAMETYPEDEFAULTFUNCTION
15:12ReservedRO0Reserved
11:0FAGC AccumulatorRW0110 0000 0000FAGC Accumulator
Table 8-81 0x0403 Line Driver Control Register (LDCTRL)
BITNAMETYPEDEFAULTFUNCTION
15:12ReservedRW1001Reserved
11:8100Base-FX Line Driver Swing SelectRW1111100Base-FX Line Driver Swing Select (peak-to-peak):

0000 = 0.533-V
0001 = 0.567-V
0010 = 0.600-V
0011 = 0.633-V
0100 = 0.667-V
0101 = 0.700-V
0110 = 0.733-V
0111 = 0.767-V
1000 = 0.800-V
1001 = 0.833-V
1010 = 0.867-V
1011 = 0.900-V
1100 = 0.933-V
1101 = 0.976-V
1110 = 1.000-V
1111 = 1.033-V (Default Setting)
7:4100Base-TX Line Driver Swing SelectRW1100100Base-TX Line Driver Swing Select (peak-to-peak):

0000 = 1.600-V
0001 = 1.633-V
0010 = 1.667-V
0011 = 1.700-V
0100 = 1.733-V
0101 = 1.767-V
0110 = 1.800-V
0111 = 1.833-V
1000 = 1.867-V
1001 = 1.900-V
1010 = 1.933-V
1011 = 1.967-V
1100 = 2.000-V (Default Setting)
1101 = 2.033-V
1110 = 2.067-V
1111 = 2.100-V
3:010Base-Te Line Driver Swing SelectRW111110Base-Te Line Driver Swing Select:

0000 = 3.200-V
0001 = 3.233-V
0010 = 3.267-V
0011 = 3.300-V
0100 = 3.333-V
0101 = 3.367-V
0110 =3.400-V
0111 = 3.433-V
1000 = 3.467-V
1001 = 3.500-V
1010 = 3.533-V
1011 = 3.567-V
1100 = 3.600-V
1101 = 3.633-V
1110 = 3.667-V
1111 = 3.700-V (Default Setting)
Table 8-82 0x0404 Line Driver Class Selection (LDCSEL)
BITNAMETYPEDEFAULTFUNCTION
15:0Line Driver Class SelectionRW00200x0020 : Reduced MLT-3 (Class B)
0x0024 : To program full MLT-3 on both Tx+ and Tx– (Class A)
Table 8-83 0x040D Auto-neg Energy Threshold Register
BITNAMETYPEDEFAULTFUNCTION
15: 5ReservedRW0000 0000 000
4:0Auto-neg Energy Threshold ValueRW0 1000Decides threshold of energy detection during auto-negotiation
Table 8-84 0x0410 DC Correction Control Register
BITNAMETYPEDEFAULTFUNCTION
15ReservedRW0Reserved
14Enable Fixed DC CorrectionRW01 = Enable Fixed Value of DC Correction
13:0ReservedRW10 0000 0000 0000
Table 8-85 0x0416 Analog Filter Control Register 1
BITNAMETYPEDEFAULTFUNCTION
15:13ReservedRW000Reserved
12:8Filter 1 cut-offRW01000Controls the cut-off frequency of filter 1
7:0ReservedRW0111 0000Reserved
Table 8-86 0x0418 Analog Equalizer Control Register
BITNAMETYPEDEFAULTFUNCTION
15:14ReservedRW00Reserved
13:8Analog Equalizer ControlRW0000 00Analog equalizer controls useful for short shielded cables
7:0ReservedRW0000 0000Reserved
Table 8-87 0x041F Analog Power Detect Control
BITNAMETYPEDEFAULTFUNCTION
15:13ReservedRW000Reserved
12Force AVDD DetectRW0Force AVDD to be detected as 3.3V
1=Force AVDD to be detected as 3.3V
0=Internal circuit detects the AVDD supply level
11:10Force AVDDIO DetectRW00Force AVDDIO to be detected as 3.3V
11 = Force AVDDIO to be detected as 3.3V
00 = Internal circuit detects the AVDDIO supply level
9:0ReservedRW00 0000 0000Reserved
For specific applications which require bypassing auto supply detection, registers 0x0421 and 0x041F can be used to program specific supply levels
Table 8-88 0x0421 Analog Power Detect Status
BITNAMETYPEDEFAULTFUNCTION
15:3ReservedRO0Reserved
2AVDD LevelRO1 for 3.3V AVDD
0 for 1.8V AVDD
AVDD level indication
1:0VDDIO LevelRO11 for 3.3V VDDIO
00 for 1.8V VDDIO
01 for 2.5V VDDIO
VDDIO level indication
Table 8-89 0x0428 Deep Power Down Control Register (DPDWN)
BITNAMETYPEDEFAULTFUNCTION
15:6ReservedRO0Reserved
5MSB 100Base-TX Idle PatternRW0MSB 100Base-TX Idle Pattern:

100Base-TX Test Mode is determined by bits \{[5] in register 0x0428, [3:0] in register 0x0027\}. The bits determine the number of 0's to follow a '1'.
0,0001 = Single '0' after a '1'
0,0010 = Two '0' after a '1'
0,0011 = Three '0' after a '1'
0,0100 = Four '0' after a '1'
0,0101 = Five '0' after a '1'
0,0110 = Six '0' after a '1'
0,0111 = Seven '0' after a '1' .
..
1,1111 = Thirty one '0' after a '1'
0,0000 = Clears the shift register
4100Base-TX Idle Pattern Test ModeRW0100Base-TX Idle Pattern Test Mode:
1 = 100Base-TX Idle Pattern Enable
0 = Normal operation

When enabled, 100Base-TX Idle Pattern is determined by bit[5] in register 0x0428 and bits[3:0] in register 0x0027.

3Deep Power Down SpeedRW0Deep Power Down Speed Selection:
1 = 50ms duration to exit Deep Power Down
0 = 100ms duration to exit Deep Power Down
2Deep Power Down EnableRW0Deep Power Down Enable:
1 = Deep Power Down activated
0 = Normal operation

Note: If set, the DP83822 enters into deep power down mode. Deep power down mode requires that IEEE Power Down be enabled first by either register access (set bit[11] = '1' in register 0x0000) or using INT/PWDN pin.

1:0ReservedRW0Reserved
Table 8-90 0x0450 DSP Configuration Register 6 (DSPCR6)
BITNAMETYPEDEFAULTFUNCTION
15:14ReservedRW00Reserved
13Equalizer Calibration BypassRW01 = Bypass equalizer calibration
12:0ReservedRW0 0001 0100 0001Reserved
Table 8-91 0x0456 General Configuration Register (GENCFG)
BITNAMETYPEDEFAULTFUNCTION
15:4ReservedRW0Reserved
3Min IPG EnableRW1Min IPG Enable:
1 = Enable Minimum Inter-Packet Gap (IPG is set to 120ns)
0 = IPG set to 0.20μs

Note:

IPGs <200ns should only be used when operating with a MII MAC IF configuration.
2:0ReservedRW0Reserved
Table 8-92 0x0460 LEDs Configuration Register #1 (LEDCFG1)
BITNAMETYPEDEFAULTFUNCTION
15:12ReservedRO0Reserved
11:8LED_1 ControlRW0101LED_1 Control:
Selects the source for LED_1.
0000 = LINK OK
0001 = RX/TX Activity
0010 = TX Activity
0011 = RX Activity
0100 = Collision
0101 = Speed, High for 100Base-TX
0110 = Speed, High for 10Base-Te
0111 = Full-Duplex
1000 = LINK OK / BLINK on TX/RX Activity
1001 = Active Stretch Signal
1010 = MII LINK (100BT+FD)
1011 = LPI Mode (EEE)
1100 = TX/RX MII Error
1101 = Link Lost
1110 = Blink for PRBS error
1111 = Reserved

Link Lost, LED remains ON until BMCR register (address 0x0001) is read.

Blink for PRBS Errors, LED remains ON for single error and remains until BICSR1 register (address 0x001B) is cleared.

7:4LED_3 Control (RX_D3)RW0101LED_3 Control:
Selects the source for RX_D3. Please reference bits[11:8] for list of sources.
3:0ReservedRW0001Reserved
Table 8-93 0x0461 IO MUX GPIO Control Register (IOCTRL)
BITNAMETYPEDEFAULTFUNCTION
15:5ReservedRW0000 0100 000Reserved
4:1MAC Impedance ControlRW1 000MAC Impedance Control:
MAC interface impedance control sets the series termination for the digital pins.
0 000 = 99.25 Ω
0 001 = 91.13 Ω
0 010 = 84.24 Ω
0 011 = 78.31 Ω
0 100 = 73.17 Ω
0 101 = 68.65 Ω
0 110 = 64.66 Ω
0 111 = 61.11 Ω
1 000 = 58.07 Ω (Default Setting)
1 001 = 55.18 Ω
1 010 = 52.57 Ω
1 011 = 50.20 Ω
1 100 = 48.03 Ω
1 101 = 46.04 Ω
1 110 = 44.20 Ω
1 111 = 42.51 Ω
0ReservedRW0Reserved
Table 8-94 0x0462 IO MUX GPIO Control Register #1 (IOCTRL1)
BITNAMETYPEDEFAULTFUNCTION
15ReservedRO0Reserved
14:12RX_D3 / GPIO_3 Clock SourceRW000Clock Source:
If RX_D3 is configured as a clock source from bits[10:8] the following field determines the reference
000 = MAC IF Clock
001 = XI Clock (Pass-Through Clock from XI pin)
010 = Internal Reference Clock: 25-MHz
011 = Reserved
100 = RMII Master Mode Reference Clock: 50-MHz
101 = Reserved
110 = Free Running Clock: 125-MHz
111 = Recovered Clock: 125-MHz

MAC IF Clock: MII Mode the clock frequency is 25-MHz, RMII Mode the clock frequency is 50-MHz; RGMII Mode the clock frequency is 25-MHz.

RMII Master Mode Reference Clock: Identical to MAC IF Clock in RMII Master Mode.

11ReservedRO0Reserved
10:8RX_D3 / GPIO_3 ControlRW000RX_D3 GPIO Configuration:
000 = Normal operation
001 = LED_3 (Default: Speed, High for 100Base-TX)
010 = WoL
011 = Clock reference according to bits[14:12]
100 = IEEE 1588 TX Indication
101 = IEEE 1588 RX Indication
110 = Constant '0'
111 = Constand '1'
7ReservedRO0Reserved
6:4LED_1 / GPIO_1 Clock SourceRW000Clock Source:
If LED_1 is configured as a clock source from bits[2:0] the following field determines the reference
000 = MAC IF Clock
001 = XI Clock (Pass-Through Clock from XI pin)
010 = Internal Reference Clock: 25-MHz
011 = Reserved
100 = RMII Master Mode Reference Clock: 50-MHz
101 = Reserved
110 = Free Running Clock: 125-MHz
111 = Recovered Clock: 125-MHz

MAC IF Clock: MII Mode the clock frequency is 25-MHz, RMII Mode the clock frequency is 50-MHz; RGMII Mode the clock frequency is 25-MHz.

RMII Master Mode Reference Clock: Identical to MAC IF Clock in RMII Master Mode.

3ReservedRO0Reserved
2:0LED_1 / GPIO_1 ControlRW, Strap000LED_1 GPIO Configuration:
000 = Tri-state
001 = LED_1 (Default: Speed, High for 100Base-TX)
010 = WoL
011 = Clock reference according to bits[6:4]
100 = IEEE 1588 TX Indication
101 = IEEE 1588 RX Indication
110 = Constant '0'
111 = Constand '1'
Table 8-95 0x0463 IO MUX GPIO Control Register #2 (IOCTRL2)
BITNAMETYPEDEFAULTFUNCTION
15:7ReservedRO0Reserved
6:4COL / GPIO_2 Clock SourceRW000Clock Source:
If COL is configured as a clock source from bits[2:0] the following field determines the reference
000 = MAC IF Clock
001 = XI Clock (Pass-Through Clock from XI pin)
010 = Internal Reference Clock: 25-MHz
011 = Reserved
100 = RMII Master Mode Reference Clock: 50-MHz
101 = Reserved
110 = Free Running Clock: 125-MHz
111 = Recovered Clock: 125-MHz

MAC IF Clock: MII Mode the clock frequency is 25-MHz, RMII Mode the clock frequency is 50-MHz; RGMII Mode the clock frequency is 25-MHz.

RMII Master Mode Reference Clock: Identical to MAC IF Clock in RMII Master Mode.

3ReservedRO0Reserved
2:0COL / GPIO_2 ControlRW000COL GPIO Configuration:
000 = Normal operation
001 = MLED (Register 0x0025)
010 = WoL
011 = Clock reference according to bits[6:4]
100 = IEEE 1588 TX Indication
101 = IEEE 1588 RX Indication
110 = Constant '0'
111 = Constand '1'
Table 8-96 0x0465 Fiber General Configuration Register (FIBER GENCFG)
BITNAMETYPEDEFAULTFUNCTION
15:1ReservedRW1111 1111 0000 000Reserved
0100Base-FX Signal Detect PolarityRW0100Base-FX Signal Detect Polarity:
1 = Signal Detect is Active LOW
0 = Signal Detect is Active HIGH

When set to Active HIGH, Link drop will occur if SD pin senses a LOW state (SD = '0').

When set to Active LOW, Link drop will occur if SD pin senses a HIGH state (SD = '1').

Note: To enable 100Base-FX Signal Detection on LED_1 (pin #24), strap SD_EN = '1'

Table 8-97 0x0467 Strap Latch-In Register #1 (SOR1)
BITNAMETYPEDEFAULTFUNCTION
15:14RX_D1 Strap ModeRO, Strap00RX_D1 Strap Mode:

00 = Mode 1
01 = Mode 2
10 = Mode 3
11 = Mode 4

Please refer to the strap section in the datasheet for information regarding PHY configuration.

Note: Bit values ('00', '01', '10', '11') are just used to indicate the Strap Mode and do not reflect the same bit sequence that is defined in the strap section of the datasheet.

13:12RX_D0 Strap ModeRO, Strap00RX_D0 Strap Mode:
Use same reference as defined by bits[15:14] in this register.
11:10COL Strap ModeRO, Strap11COL Strap Mode:
Use same reference as defined by bits[15:14] in this register.
9:8RX_ER Strap ModeRO, Strap11RX_ER Strap Mode:
Use same reference as defined by bits[15:14] in this register.
7:6CRS Strap ModeRO, Strap11CRS Strap Mode:
Use same reference as defined by bits[15:14] in this register.
5:4RX_DV Strap ModeRO, Strap00RX_DV Strap Mode:
Use same reference as defined by bits[15:14] in this register.
3:2ReservedRO00Reserved
1:0LED_0 Strap ModeRO, Strap11LED_0 Strap Mode:

00 = Mode 1
01 = Reserved
10 = Reserved
11 = Mode 4

Please refer to the strap section in the datasheet for information regarding PHY configuration.

Note: Bit values ('00', '01', '10', '11') are just used to indicate the Strap Mode and do not reflect the same bit sequence that is defined in the strap section of the datasheet.

Table 8-98 0x0468 Strap Latch-In Register #2 (SOR2)
BITNAMETYPEDEFAULTFUNCTION
15:4ReservedRO0Reserved
3:2RX_D3 Strap ModeRO, Strap00RX_D3 Strap Mode:
Use same reference as defined by bits[15:14] in register 0x0467.
1:0RX_D2 Strap ModeRO, Strap00RX_D2 Strap Mode:
Use same reference as defined by bits[15:14] in register 0x0467.
Table 8-99 0x0469 LEDs Configuration Register #2 (LEDCFG2)
BITNAMETYPEDEFAULTFUNCTION
15:11ReservedRO0Reserved
10LED_1 PolarityRW0LED_1 Polarity:
1 = Active High
0 = Active Low
Value depends upon pull configuration on LED_1 pin.
9LED_1 Force Override ValueRW0LED_1 Force Override Value:
1 = LED_1 forced High
0 = LED_1 forced Low
8LED_1 Force Override EnableRW0LED_1 Force Override Enable:
1 = Enable Force Override
0 = Disable Force Override

When enabled, bit[9] in this register determines state of LED_1.

7ReservedRO0Reserved
6LED_3 PolarityRW1LED_3 Polarity:
1 = Active High
0 = Active Low
5LED_3 Force Override ValueRW0LED_3 Force Override Value:
1 = RX_D3 forced High
0 = RX_D3 forced Low
4LED_3 Force Override EnableRW0LED_3 Force Override Enable:
1 = Enable Force Override
0 = Disable Force Override

When enabled, bit[5] in this register determines state of RX_D3.

3:0ReservedRO0Reserved
Table 8-100 0x04A0 Receive Configuration Register (RXFCFG)
BITNAMETYPEDEFAULTFUNCTION
15:14Bit Nibble SwapRW00Bit Nibble Swap:
00 = Normal order, no swap (RXD[3:0])
01 = Swap bits order (RXD[0:3])
10 = Swap nibbles order (RXD[3:0] , RXD[7:4])
11 = Swap bits order in each nibble (RXD[4:7] , RXD[0:3])
13SFD ByteRW0SFD Byte Search:
1 = SFD is 0x5D (i.e. Receive module searches for 0x5D)
0 = SFD is 0xD5 (i.e. Receive module searches for 0xD5)
12CRC GateRW1CRC Gate:
1 = Bad CRC gates Magic Packet and Pattern Indications
0 = Bad CRC does not gate Magic Packet or Pattern Indications

If Magic Packet has Bad CRC there will be no indication (status, interrupt, GPIO) when enabled.

11WoL Level Change Indication ClearW, SC0WoL Level Change Indication Clear:
If WoL Indication is set for Level change mode, this bit clears the level upon a write.
10:9WoL Pulse Indication SelectRW00WoL Pulse Indication Select:
Only valid when WoL Indication is set for Pulse mode.

00 = 8 clock cycles (of 125-MHz clock)
01 = 16 clock cycles
10 = 32 clock cycles
11 = 64 clock cycles
8WoL Indication SelectRW0WoL Indication Select:
1 = Level change mode
0 = Pulse mode
7WoL EnableRW0WoL Enable:
1 = Enable Wake-on-LAN (WoL)
0 = Normal operation
6Bit Mask FlagRW0Bit Mask Flag
5Secure-ON EnableRW0Enable Secure-ON password for Magic Packets
4:2ReservedRW0Reserved
1WoL Pattern EnableRW0Enable Interrupt upon reception of packet with configured pattern
0WoL Magic Packet EnableRW0Enable Interrupt upon reception of Magic Packet
Table 8-101 0x04A1 Receive Status Register (RXFS)
BITNAMETYPEDEFAULTFUNCTION
15:13ReservedRO0Reserved
12WoL Interrupt SourceRW0WoL Interrupt Source:
Source of Interrupt for bit[1] of register 0x0013.
1 = WoL Interrupt
0 = Data Polarity Interrupt

When enabling WoL, this bit is automatically set to WoL Interrupt.

11:8ReservedRO0Reserved
7SFD ErrorRO, LH, SC0SFD Error:
1 = Packet with SFD error
0 = No SFD error
6Bad CRCRO, LH, SC0Bad CRC:
1 = Bad CRC was received
0 = No bad CRC received
5Secure-On Hack FlagRO, LH, SC0Secure-ON Hack Flag:
1 = Invalid Password detected in Magic Packet
0 = Valid Secure-ON Password
4:2ReservedRO, LH, SC0Reserved
1WoL Pattern StatusRO, LH, SC0WoL Pattern Status:
1 = Valid packet with configured pattern received
0 = No valid packet with configured pattern received
0WoL Magic Packet StatusRO, LH, SC0WoL Magic Packet Status:
1 = Valid Magic Packet received
0 = No valid Magic Packet received
Table 8-102 0x04A2 Receive Perfect Match Data Register #1 (RXFPMD1)
BITNAMETYPEDEFAULTFUNCTION
15:8MAC Destination Address Byte 4RW0Perfect Match Data:
Configured for MAC Destination Address
7:0MAC Destination Address Byte 5RW0Perfect Match Data:
Configured for MAC Destination Address
Table 8-103 0x04A3 Receive Perfect Match Data Register #2 (RXFPMD2)
BITNAMETYPEDEFAULTFUNCTION
15:8MAC Destination Address Byte 2RW0Perfect Match Data:
Configured for MAC Destination Address
7:0MAC Destination Address Byte 3RW0Perfect Match Data:
Configured for MAC Destination Address
Table 8-104 0x04A4 Receive Perfect Match Data Register #3 (RXFPMD3)
BITNAMETYPEDEFAULTFUNCTION
15:8MAC Destination Address Byte 0RW0Perfect Match Data:
Configured for MAC Destination Address
7:0MAC Destination Address Byte 1RW0Perfect Match Data:
Configured for MAC Destination Address
Table 8-105 0x04A5 Receive Secure-ON Password Register #1 (RXFSOP1)
BITNAMETYPEDEFAULTFUNCTION
15:8Secure-ON Password Byte 1RW0Secure-ON Password Select:
Secure-ON password for Magic Packets
7:0Secure-ON Password Byte 0RW0Secure-ON Password Select:
Secure-ON password for Magic Packets
Table 8-106 0x04A6 Receive Secure-ON Password Register #2 (RXFSOP2)
BITNAMETYPEDEFAULTFUNCTION
15:8Secure-ON Password Byte 3RW0Secure-ON Password Select:
Secure-ON password for Magic Packets
7:0Secure-ON Password Byte 2RW0Secure-ON Password Select:
Secure-ON password for Magic Packets
Table 8-107 0x04A7 Receive Secure-ON Password Register #3 (RXFSOP3)
BITNAMETYPEDEFAULTFUNCTION
15:8Secure-ON Password Byte 5RW0Secure-ON Password Select:
Secure-ON password for Magic Packets
7:0Secure-ON Password Byte 4RW0Secure-ON Password Select:
Secure-ON password for Magic Packets
Table 8-108 0x04A8 Receive Pattern Register #1 (RXFPAT1)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 1RW0Pattern Configuration:
Configures byte 1 of the pattern
7:0Pattern Byte 0RW0Pattern Configuration:
Configures byte 0 of the pattern
Table 8-109 0x04A9 Receive Pattern Register #2 (RXFPAT2)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 3RW0Pattern Configuration:
Configures byte 3 of the pattern
7:0Pattern Byte 2RW0Pattern Configuration:
Configures byte 2 of the pattern
Table 8-110 0x04AA Receive Pattern Register #3 (RXFPAT3)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 5RW0Pattern Configuration:
Configures byte 5 of the pattern
7:0Pattern Byte 4RW0Pattern Configuration:
Configures byte 4 of the pattern
Table 8-111 0x04AB Receive Pattern Register #4 (RXFPAT4)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 7RW0Pattern Configuration:
Configures byte 7 of the pattern
7:0Pattern Byte 6RW0Pattern Configuration:
Configures byte 6 of the pattern
Table 8-112 0x04AC Receive Pattern Register #5 (RXFPAT5)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 9RW0Pattern Configuration:
Configures byte 9 of the pattern
7:0Pattern Byte 8RW0Pattern Configuration:
Configures byte 8 of the pattern
Table 8-113 0x04AD Receive Pattern Register #6 (RXFPAT6)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 11RW0Pattern Configuration:
Configures byte 11 of the pattern
7:0Pattern Byte 10RW0Pattern Configuration:
Configures byte 10 of the pattern
Table 8-114 0x04AE Receive Pattern Register #7 (RXFPAT7)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 13RW0Pattern Configuration:
Configures byte 13 of the pattern
7:0Pattern Byte 12RW0Pattern Configuration:
Configures byte 12 of the pattern
Table 8-115 0x04AF Receive Pattern Register #8 (RXFPAT8)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 15RW0Pattern Configuration:
Configures byte 15 of the pattern
7:0Pattern Byte 14RW0Pattern Configuration:
Configures byte 14 of the pattern
Table 8-116 0x04B0 Receive Pattern Register #9 (RXFPAT9)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 17RW0Pattern Configuration:
Configures byte 17 of the pattern
7:0Pattern Byte 16RW0Pattern Configuration:
Configures byte 16 of the pattern
Table 8-117 0x04B1 Receive Pattern Register #10 (RXFPAT10)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 19RW0Pattern Configuration:
Configures byte 19 of the pattern
7:0Pattern Byte 18RW0Pattern Configuration:
Configures byte 18 of the pattern
Table 8-118 0x04B2 Receive Pattern Register #11 (RXFPAT11)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 21RW0Pattern Configuration:
Configures byte 21 of the pattern
7:0Pattern Byte 20RW0Pattern Configuration:
Configures byte 20 of the pattern
Table 8-119 0x04B3 Receive Pattern Register #12 (RXFPAT12)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 23RW0Pattern Configuration:
Configures byte 23 of the pattern
7:0Pattern Byte 22RW0Pattern Configuration:
Configures byte 22 of the pattern
Table 8-120 0x04B4 Receive Pattern Register #13 (RXFPAT13)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 25RW0Pattern Configuration:
Configures byte 25 of the pattern
7:0Pattern Byte 24RW0Pattern Configuration:
Configures byte 24 of the pattern
Table 8-121 0x04B5 Receive Pattern Register #14 (RXFPAT14)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 27RW0Pattern Configuration:
Configures byte 27 of the pattern
7:0Pattern Byte 26RW0Pattern Configuration:
Configures byte 26 of the pattern
Table 8-122 0x04B6 Receive Pattern Register #15 (RXFPAT15)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 29RW0Pattern Configuration:
Configures byte 29 of the pattern
7:0Pattern Byte 28RW0Pattern Configuration:
Configures byte 28 of the pattern
Table 8-123 0x04B7 Receive Pattern Register #16 (RXFPAT16)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 31RW0Pattern Configuration:
Configures byte 31 of the pattern
7:0Pattern Byte 30RW0Pattern Configuration:
Configures byte 30 of the pattern
Table 8-124 0x04B8 Receive Pattern Register #17 (RXFPAT17)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 33RW0Pattern Configuration:
Configures byte 33 of the pattern
7:0Pattern Byte 32RW0Pattern Configuration:
Configures byte 32 of the pattern
Table 8-125 0x04B9 Receive Pattern Register #18 (RXFPAT18)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 35RW0Pattern Configuration:
Configures byte 35 of the pattern
7:0Pattern Byte 34RW0Pattern Configuration:
Configures byte 34 of the pattern
Table 8-126 0x04BA Receive Pattern Register #19 (RXFPAT19)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 37RW0Pattern Configuration:
Configures byte 37 of the pattern
7:0Pattern Byte 36RW0Pattern Configuration:
Configures byte 36 of the pattern
Table 8-127 0x04BB Receive Pattern Register #20 (RXFPAT20)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 39RW0Pattern Configuration:
Configures byte 39 of the pattern
7:0Pattern Byte 38RW0Pattern Configuration:
Configures byte 38 of the pattern
Table 8-128 0x04BC Receive Pattern Register #21 (RXFPAT21)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 41RW0Pattern Configuration:
Configures byte 41 of the pattern
7:0Pattern Byte 40RW0Pattern Configuration:
Configures byte 40 of the pattern
Table 8-129 0x04BD Receive Pattern Register #22 (RXFPAT22)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 43RW0Pattern Configuration:
Configures byte 43 of the pattern
7:0Pattern Byte 42RW0Pattern Configuration:
Configures byte 42 of the pattern
Table 8-130 0x04BE Receive Pattern Register #23 (RXFPAT23)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 45RW0Pattern Configuration:
Configures byte 45 of the pattern
7:0Pattern Byte 44RW0Pattern Configuration:
Configures byte 44 of the pattern
Table 8-131 0x04BF Receive Pattern Register #24 (RXFPAT24)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 47RW0Pattern Configuration:
Configures byte 47 of the pattern
7:0Pattern Byte 46RW0Pattern Configuration:
Configures byte 46 of the pattern
Table 8-132 0x04C0 Receive Pattern Register #25 (RXFPAT25)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 49RW0Pattern Configuration:
Configures byte 49 of the pattern
7:0Pattern Byte 48RW0Pattern Configuration:
Configures byte 48 of the pattern
Table 8-133 0x04C1 Receive Pattern Register #26 (RXFPAT26)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 51RW0Pattern Configuration:
Configures byte 51 of the pattern
7:0Pattern Byte 50RW0Pattern Configuration:
Configures byte 50 of the pattern
Table 8-134 0x04C2 Receive Pattern Register #27 (RXFPAT27)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 53RW0Pattern Configuration:
Configures byte 53 of the pattern
7:0Pattern Byte 52RW0Pattern Configuration:
Configures byte 52 of the pattern
Table 8-135 0x04C3 Receive Pattern Register #28 (RXFPAT28)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 55RW0Pattern Configuration:
Configures byte 55 of the pattern
7:0Pattern Byte 54RW0Pattern Configuration:
Configures byte 54 of the pattern
Table 8-136 0x04C4 Receive Pattern Register #29 (RXFPAT29)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 57RW0Pattern Configuration:
Configures byte 57 of the pattern
7:0Pattern Byte 56RW0Pattern Configuration:
Configures byte 56 of the pattern
Table 8-137 0x04C5 Receive Pattern Register #30 (RXFPAT30)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 59RW0Pattern Configuration:
Configures byte 59 of the pattern
7:0Pattern Byte 58RW0Pattern Configuration:
Configures byte 58 of the pattern
Table 8-138 0x04C6 Receive Pattern Register #31 (RXFPAT31)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 61RW0Pattern Configuration:
Configures byte 61 of the pattern
7:0Pattern Byte 60RW0Pattern Configuration:
Configures byte 60 of the pattern
Table 8-139 0x04C7 Receive Pattern Register #32 (RXFPAT32)
BITNAMETYPEDEFAULTFUNCTION
15:8Pattern Byte 63RW0Pattern Configuration:
Configures byte 63 of the pattern
7:0Pattern Byte 62RW0Pattern Configuration:
Configures byte 62 of the pattern
Table 8-140 0x04C8 Receive Pattern Byte Mask Register #1 (RXFPBM1)
BITNAMETYPEDEFAULTFUNCTION
15:0Mask Bytes 0 to 15RW0Pattern Byte Mask Configuration:
Configures masks for bytes 0 to 15.
For each byte '1' means it is masked.
Table 8-141 0x04C9 Receive Pattern Byte Mask Register #2 (RXFPBM2)
BITNAMETYPEDEFAULTFUNCTION
15:0Mask Bytes 16 to 31RW0Pattern Byte Mask Configuration:
Configures masks for bytes 16 to 31.
For each byte '1' means it is masked.
Table 8-142 0x04CA Receive Pattern Byte Mask Register #3 (RXFPBM3)
BITNAMETYPEDEFAULTFUNCTION
15:0Mask Bytes 32 to 47RW0Pattern Byte Mask Configuration:
Configures masks for bytes 32 to 47.
For each byte '1' means it is masked.
Table 8-143 0x04CB Receive Pattern Byte Mask Register #4 (RXFPBM4)
BITNAMETYPEDEFAULTFUNCTION
15:0Mask Bytes 48 to 63RW0Pattern Byte Mask Configuration:
Configures masks for bytes 48 to 63.
For each byte '1' means it is masked.
Table 8-144 0x04CC Receive Pattern Control Register (RXFPATC)
BITNAMETYPEDEFAULTFUNCTION
15:6ReservedRO0Reserved
5:0Pattern Start PointRW01100Pattern Start Point:
Number of bytes after SFD where comparison begins on RX packets to the configured pattern.

00000 = Start compare on 1st byte after SFD
00001 = Start compare on 2nd byte after SFD
...
01100 = Start compare on 13th byte (Default)
Default setting is 0xC, which means the pattern comparision will begin after source and destination addresses since they are each 6 bytes.
Table 8-145 0x04D0 Energy Efficient Ethernet Configuration Register #2 (EEECFG2)
BITNAMETYPEDEFAULTFUNCTION
15ReservedRO0Reserved
14TX_ER for LPI RequestRW0TX_ER for LPI Request:
1 = TX_ER used for LPI Request
0 = TX_ER not used for LPI Request
13:7ReservedRO00 0011 0Reserved
6:5TX_ER Pin SelectRW00TX_ER Pin Select:
00 = No Pin Selected
01 = INT/PWDN
10 = COL/GPIO
11 = No Pin Selected
4:0ReservedRO0 0010Reserved
Table 8-146 0x04D1 Energy Efficient Ethernet Configuration Register #2 (EEECFG3)
BITNAMETYPEDEFAULTFUNCTION
15:4ReservedRW0000 0001 1000Reserved
3EEE Capabilities BypassRW1EEE Advertise Bypass:
1 = Bit [0] determines EEE Auto-Negotiation Abilities
0 = MMD3 and MMD7 determine EEE Auto-Negotiation Abilities

Allows for EEE Advertisment during Auto-Negotiation to be determined by bit[0] in register 0x04D1 rather than the Next Page Registers (Register 0x003C and Register 0x003D in MMD7).

2EEE Next Page DisableRW0EEE Next Page Disable:
1 = Reception of EEE Next Pages is disabled
0 = Reception of EEE Next Pages is enabled
1EEE RX Path ShutdownRW1EEE RX Path Shutdown:
1= Enable shutdown of Analog RX path at LPI_Quiet
0 = Analog RX path is active during LPI_Quiet
0EEE Capabilities EnableRW, Strap1EEE Capabilities Enable:
1 = PHY supports EEE capabilities
0 = PHY does not support EEE

When enabled, Auto-Negotiation will negotiate to EEE as defined by register 0x003C and register 0x003D in MMD7.

When disabled, register 0x0014 in MMD3, register 0x003C and register 0x003D in MMD7 are ignored.

Bit should be written to 0 (irrespective of strap used) to disable EEE.

Table 8-147 0x04D4 TLOOP Bandwidth Control Register 1 (TLBCR1)
BITNAMETYPEDEFAULTFUNCTION
15:0ReservedRW0111 0010 0010 0000Reserved
Table 8-148 0x04D5 TLOOP Bandwidth Control Register 2 (TLBCR2)
BITNAMETYPEDEFAULTFUNCTION
15:0ReservedRW1111 1011 1100 0001Reserved
Table 8-149 0x04D6 TLOOP Bandwidth Control Register 3 (TLBCR3)
BITNAMETYPEDEFAULTFUNCTION
15:0ReservedRW0000 0001 1100 0001Reserved
Table 8-150 0x3000 MMD3 PCS Control Register #1 (MMD3_PCS_CTRL_1)
BITNAMETYPEDEFAULTFUNCTION
15PCS ResetRW, SC0PCS Reset:
1 = Soft Reset of MMD3, MMD7 and PCS registers
0 = Normal operation

Reset clears MMD3, MMD7 and PCS registers. Reset does not clear Vendor Specific Registers (DEVAD = 31).

14:11ReservedRO000 0Reserved
10RX Clock StoppableRW1RX Clock Stoppable:
1 = Receive Clock stoppable during LPI
0 = Receive Clock not stoppable
9:0ReservedRO00 0000 0000Reserved
Table 8-151 0x3001 MMD3 PCS Status Register #1 (MMD3_PCS_STATUS_1)
BITNAMETYPEDEFAULTFUNCTION
15:12ReservedRO0Reserved
11TX LPI ReceivedRO0TX LPI Received:
1 = TX PCS has received LPI
0 = LPI not received
10RX LPI ReceivedRO0RX LPI Received:
1 = RX PCS has received LPI
0 = LPI not received
9TX LPI IndicationRO0TX LPI Indication:
1 = TX PCS is currently receiving LPI
0 = TX PCS is not currently receiving LPI
8RX LPI IndicationRO0RX LPI Indication:
1 = RX PCS is currently receiving LPI
0 = RX PCS is not currenly receiving LPI
7ReservedRO0Reserved
6TX Clock StoppableRO1TX Clock Stoppable:
1 = MAC may stop clock during LPI
0 = TX Clock is not stoppable
5:0ReservedRO0Reserved
Table 8-152 0x3014 MMD3 Energy Efficient Ethernet Capability Register (MMD3_EEE_CAPABILITY)
BITNAMETYPEDEFAULTFUNCTION
15:3ReservedRO0Reserved
2EEE 1Gbps EnableRO0EEE 1Gbps Enable:
1 = EEE is supported for 1000Base-T
0 = EEE is not supported for 1000Base-T
1EEE 100Mbps EnableRO1EEE 100Mbps Enable:
1 = EEE is supported for 100Base-TX
0 = EEE is not supported for 100Base-TX
0ReservedRO0Reserved
Table 8-153 0x3016 MMD3 Wake Error Counter Register (MMD3_WAKE_ERR_CNT)
BITNAMETYPEDEFAULTFUNCTION
15:0EEE Wake Error CounterRO, LH0EEE Wake Error Counter:
This register counts the wake time faults where the PHY fails to complete its normal wake sequence within the time required for the specific PHY type.

This counter is cleared after a read and holds at all ones in the case of overflow. PCS Reset also clears this register.

Table 8-154 0x703C MMD7 Energy Efficient Ethernet Advertisement Register (MMD7_EEE_ADVERTISEMENT)
BITNAMETYPEDEFAULTFUNCTION
15:2ReservedRO0Reserved
1Advertise 100Base-TX EEERW,Strap1Advertise 100Base-TX EEE:
1 = Energy Efficient Ethernet is advertised for 100Base-TX
0 = Energy Efficient Ethernet is not advertised
0ReservedRO0Reserved
Table 8-155 0x703D MMD7 Energy Efficient Ethernet Link Partner Ability Register (MMD7_EEE_LP_ABILITY)
BITNAMETYPEDEFAULTFUNCTION
15:2ReservedRO0Reserved
1Link Partner EEE CapabilityRO0Link Partner EEE Capability:
1 = Link Partner is advertising EEE capability for 100Base-TX
0 = Link Partner is not advertising EEE capability for 100Base-TX
0ReservedRO0Reserved