The DP83822 incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification from the RMII consortium. The purpose of this interface is to provide a reduced pin count alternative to the IEEE 802.3u MII as specified in Clause 22. Architecturally, the RMII specification provides an additional reconciliation layer on either side of the MII, but can be implemented in the absence of an MII. The DP83822 offers two types of RMII operations: RMII Slave and RMII Master. In RMII Slave operation, the DP83822 operates off of a 50-MHz CMOS-level oscillator connected to the XI pin and shares the same clock as the MAC. In RMII Master operation, the DP83822 operates off of either a 25-MHz CMOS-level oscillator connected to XI pin or a 25-MHz crystal connected across XI and XO pins. A 50-MHz output clock referenced from any of the three DP83822 GPIOs is connected to the MAC.
If RMII Master mode is configured through bootstraps, a 50-MHz output clock will automatically be enabled on RX_D3 (GPIO3).
The RMII specification has the following characteristics:
In this mode, data transfers are two bits for every clock cycle using the internal 50-MHz reference clock for both transmit and receive paths.
The RMII signals are summarized below:
|Transmit and Receive Signals||TX_EN|
Data on TX_D[1:0] are latched at the PHY with reference to the clock edges on the XI pin. Data on RX_D[1:0] are latched at the MAC with reference to the same clock edges on the XI pin. RMII operates at the same speed in 10BASE-Te, 100BASE-TX and 100BASE-FX. In 10BASE-Te the data is 10 times slower than the reference clock, so transmit data is sampled every 10 clock cycles. Likewise, receive data is generated on every 10th clock so that an attached MAC device can sample the data every 10 clock cycles.
In addition, RMII mode supplies an RX_DV signal that allows a simpler method of recovering receive data without the need to separate RX_DV from the CRS_DV indication. RX_ER is also supported even though it is not required by the RMII specification.
RMII includes a programmable elastic buffer to adjust for the frequency differences between the reference clock and the recovered receive clock. The programmable elastic buffer minimizes internal propagation delay based on expected maximum packet size and clock accuracy.
Table below indicates how to program the buffer FIFO based on the expected maximum packet size and clock accuracy. It assumes that the RMII reference clock and the far-end transmitter clock have the same accuracy.
|RECOMMENDED PACKET SIZE
AT ±50 ppm
|RECOMMENDED PACKET SIZE
AT ±100 ppm
|1 (4-bits)||2 bits||2400 bytes||1200 bytes|
|2 (8-bits)||6 bits||7200 bytes||3600 bytes|
|3 (12-bits)||10 bits||12000 bytes||6000 bytes|
|4 (16-bits)||14 bits||16800 bytes||8400 bytes|