SNLS638A December 2018 – August 2019 DP83825I
The DP83825I incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification v1.2. The purpose of this interface is to provide a reduced pin count alternative to the IEEE 802.3 MII as specified in Clause 22. Architecturally, the RMII specification provides an additional reconciliation layer on either side of the MII, but can be implemented in the absence of an MII. The DP83825I offers two types of RMII operations: RMII Slave and RMII Master. In RMII Master operation, the DP83825I operates off either a 25-MHz CMOS-level oscillator connected to XI pin or a 25-MHz crystal connected across XI and XO pins. A 50-MHz output clock referenced from DP83825I can be connected to the MAC. In RMII Slave operation, the DP83825I operates off of a 50-MHz CMOS-level oscillator connected to the XI pin and shares the same clock as the MAC. Alternatively, in RMII Slave mode, the PHY can run from 50MHz clock provided by the Host MAC.
The RMII specification has the following characteristics:
In this mode, data transfers are two bits for every clock cycle using the internal 50-MHz reference clock for both transmit and receive paths.
The RMII signals are summarized in Table 1:
|Receive Data Lines||TX_D[1:0]|
|Transmit Data Lines||RX_D[1:0]|
|Receive Control Signal||TX_EN|
|Transmit Control Signal||CRS_DV|
Data on TX_D[1:0] are latched at the PHY with reference to the clock edges on the XI pin. Data on RX_D[1:0] are latched at the MAC with reference to the same clock edges on the XI pin.
In addition, CRX_DV can be configured as RX_DV signal. It allows a simpler method of recovering received data without the need to separate RX_DV from the CRS_DV indication.