SNLS647G december   2019  – july 2023 DP83826E , DP83826I

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Mode Comparison Tables
  7. 6 Pin Configuration and Functions (ENHANCED Mode)
  8. 7 Pin Configuration and Functions (BASIC Mode)
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Timing Diagrams
    8. 8.8 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Auto-Negotiation (Speed/Duplex Selection)
      2. 9.3.2  Auto-MDIX Resolution
      3. 9.3.3  Energy Efficient Ethernet
        1. 9.3.3.1 EEE Overview
        2. 9.3.3.2 EEE Negotiation
      4. 9.3.4  EEE for Legacy MACs Not Supporting 802.3az
      5. 9.3.5  Wake-on-LAN Packet Detection
        1. 9.3.5.1 Magic Packet Structure
        2. 9.3.5.2 Magic Packet Example
        3. 9.3.5.3 Wake-on-LAN Configuration and Status
      6. 9.3.6  Low Power Modes
        1. 9.3.6.1 Active Sleep
        2. 9.3.6.2 IEEE Power-Down
        3. 9.3.6.3 Deep Power Down State
      7. 9.3.7  RMII Repeater Mode
      8. 9.3.8  Clock Output
      9. 9.3.9  Media Independent Interface (MII)
      10. 9.3.10 Reduced Media Independent Interface (RMII)
      11. 9.3.11 Serial Management Interface
        1. 9.3.11.1 Extended Register Space Access
        2. 9.3.11.2 Write Address Operation
        3. 9.3.11.3 Read Address Operation
        4. 9.3.11.4 Write (No Post Increment) Operation
        5. 9.3.11.5 Read (No Post Increment) Operation
        6. 9.3.11.6 Example Write Operation (No Post Increment)
      12. 9.3.12 100BASE-TX
        1. 9.3.12.1 100BASE-TX Transmitter
          1. 9.3.12.1.1 Code-Group Encoding and Injection
          2. 9.3.12.1.2 Scrambler
          3. 9.3.12.1.3 NRZ to NRZI Encoder
          4. 9.3.12.1.4 Binary to MLT-3 Converter
        2. 9.3.12.2 100BASE-TX Receiver
      13. 9.3.13 10BASE-Te
        1. 9.3.13.1 Squelch
        2. 9.3.13.2 Normal Link Pulse Detection and Generation
        3. 9.3.13.3 Jabber
        4. 9.3.13.4 Active Link Polarity Detection and Correction
      14. 9.3.14 Loopback Modes
        1. 9.3.14.1 Near-end Loopback
        2. 9.3.14.2 MII Loopback
        3. 9.3.14.3 PCS Loopback
        4. 9.3.14.4 Digital Loopback
        5. 9.3.14.5 Analog Loopback
        6. 9.3.14.6 Far-End (Reverse) Loopback
      15. 9.3.15 BIST Configurations
      16. 9.3.16 Cable Diagnostics
        1. 9.3.16.1 Time Domain Reflectometry (TDR)
        2. 9.3.16.2 Fast Link-Drop Functionality
      17. 9.3.17 LED and GPIO Configuration
    4. 9.4 Programming
      1. 9.4.1 Hardware Bootstraps Configuration
        1. 9.4.1.1 DP83826 Bootstrap Configurations (ENHANCED Mode)
          1. 9.4.1.1.1 Bootstraps for PHY Address
        2. 9.4.1.2 DP83826 Strap Configuration (BASIC Mode)
          1. 9.4.1.2.1 Bootstraps for PHY Address
    5. 9.5 Register Maps
      1. 9.5.1 DP83826 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Twisted-Pair Interface (TPI) Network Circuit
      2. 10.2.2 Transformer Recommendations
      3. 10.2.3 Capacitive DC Blocking
      4. 10.2.4 Design Requirements
        1. 10.2.4.1 Clock Requirements
          1. 10.2.4.1.1 Oscillator
          2. 10.2.4.1.2 Crystal
      5. 10.2.5 Detailed Design Procedure
        1. 10.2.5.1 MII Layout Guidelines
        2. 10.2.5.2 RMII Layout Guidelines
        3. 10.2.5.3 MDI Layout Guidelines
      6. 10.2.6 Application Curves
  12. 11Power Supply Recommendations
  13. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Signal Traces
      2. 12.1.2 Return Path
      3. 12.1.3 Transformer Layout
      4. 12.1.4 Metal Pour
      5. 12.1.5 PCB Layer Stacking
        1. 12.1.5.1 Layout Example
  14. 13Device and Documentation Support
    1. 13.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  15. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 Electrical Characteristics

Over operating free-air temperature range  with VDDA3V3 = 3V3 (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IEEE Tx Conformance (100BaseTx)
Differential Output Voltage 950   1050 mV
IEEE Tx Conformance (10BaseTe)
Output Differential Voltage (2) 1.54 1.75 1.96 V
Power consumption Baseline (Active mode, 50% Traffic, Packet Size : 1518, Random Content, 150 meter Cable)
I(VDDA3V3=3V3) MII (100BaseTx) 45 53 mA
MII (10BaseTe) 35 46 mA
RMII Master (100BaseTx) 45 53 mA
RMII Master (10BaseTe) 35 46 mA
RMII Slave (100BaseTx) 45 53 mA
RMII Slave (10BaseTe) 35 46 mA
I(VDDIO=3V3) MII (100BaseTx) 8 14 mA
MII (10BaseTe) 5 12 mA
RMII Master (100BaseTx) 9 14 mA
RMII Master (10BaseTe) 9 12 mA
RMII Slave (100BaseTx) 7 8.5 mA
RMII Slave (10BaseTe) 5 6 mA
I(VDDIO=1V8) MII (100BaseTx) 5 7 mA
MII (10BaseTe) 3 6 mA
RMII Master (100BaseTx) 5 7 mA
RMII Master (10BaseTe) 5 6 mA
RMII Slave (100BaseTx) 3 6 mA
RMII Slave (10BaseTe) 2 3 mA
Power consumption ( Active mode worst case, 100% Traffic, Packet Size : 1518, Random Content, 150 meter Cable)
I(VDDA3V3=3V3) MII (100BaseTx) 44 55 mA
MII (10BaseTe) 35 48 mA
RMII Master (100BaseTx) 44 55 mA
RMII Master (10BaseTe) 35 48 mA
RMII Slave (100BaseTx) 44 55 mA
RMII Slave (10BaseTe) 35 48 mA
I(VDDIO=3V3) MII (100BaseTx) 10 15 mA
MII (10BaseTe) 5 12 mA
RMII Master (100BaseTx) 11 15 mA
RMII Master (10BaseTe) 9 12 mA
RMII Slave (100BaseTx) 8 12 mA
RMII Slave (10BaseTe) 5 10 mA
I(VDDIO=1V8) MII (100BaseTx) 6 9 mA
MII (10BaseTe) 2 6 mA
RMII Master (100BaseTx) 6 9 mA
RMII Master (10BaseTe) 5 7 mA
RMII Slave (100BaseTx) 4 8 mA
RMII Slave (10BaseTe) 2 6 mA
Power Consumption (Low power modes)
I(AVDD3V3=3V3) 100 BaseTx EEE mode 100 BaseTx link in EEE mode with LPIs ON 15 mA
IEEE Power Down 11 mA
Active Sleep 18 mA
RESET 12.5 mA
I(VDDIO=3V3) 100 BaseTx EEE mode 100 BaseTx link in EEE mode with LPIs ON 6 mA
I(VDDIO=3V3) IEEE Power Down 10.5 mA
I(VDDIO=3V3) Active Sleep 10.5 mA
I(VDDIO=3V3) RESET 10.5 mA
I(VDDIO=1V8) 100 BaseTx EEE mode 100 BaseTx link in EEE mode with LPIs ON 4 mA
I(VDDIO=1V8) IEEE Power Down 5.5 mA
I(VDDIO=1V8) Active Sleep 5.5 mA
I(VDDIO=1V8) RESET 5.5 mA
Bootstrap DC Characteristics (2 Level)
VIH_3v3 High Level Bootstrap Threshold : 3V3 1.3 V
VIL_3v3 Low Level Bootstrap Threshold : 3V3 0.6 V
VIH_1v8 High Level Bootstrap Threshold:1V8 1.3 V
VIL_1v8 Low Level Bootstrap Threshold :1V8 0.6 V
Crystal oscillator
Load Capacitance 15 30 pF
IO
3V3 High Level Input Voltage VDDIO = 3.3V ±10% 1.7 V
Low Level Input Voltage VDDIO = 3.3V ±10% 0.8 V
High Level Output Voltage IOH = -2mA, VDDIO = 3.3V ±10% 2.4 V
Low Level Output Voltage IOL = 2mA, VDDIO = 3.3V ±10% 0.8 V
1V8 High Level Input Voltage VDDIO = 1.8V ±10% 0.65 x VDDIO  V
Low Level Input Voltage VDDIO = 1.8V ±10% 0.35 x VDDIO  V
High Level Output Voltage IOH = -2mA, VDDIO = 1.8V ±10% VDDIO -
0.45		 V
Low Level Output Voltage IOL = 2mA, VDDIO = 1.8V ±10% 0.45 V
Iih (VIN=VCC) TA = -40℃ to 85℃, VIN=VDDIO  15 uA
Iih (VIN=VCC) TA = -40℃ to 105℃, VIN=VDDIO  25  uA
Iil (VIN=GND) TA = -40℃ to 85℃, VIN=GND  15 uA
Iil (VIN=GND) TA = -40℃ to 105℃, VIN=GND  25  uA
Iozh Tri-state Output High Current ( -40 to 85C) -15  15 uA
Iozh Tri-state Output High Current ( -40 to 105C) -25  25  uA
Iozl Tri-state Output Low Current ( -40 to 85C) -15 15 uA
Iozl Tri-state Output Low Current ( -40 to 105C) -25 25 uA
R Pull Down Internal Pull Down Resistor 7.5 10 12.5 kΩ
R Pull UP Internal Pull Up Resistor 7.5 10 12.5 kΩ
CIN Input Capacitance XI 1 pF
CIN Input Capacitance INPUT PINS 5 pF
COUT Output Capacitance XO Input Capacitance INPUT PINS 1 pF
COUT Output Capacitance OUTPUT PINS Output Capacitance XO 5 pF
XI input osc clock common mode VDDIO 1V8 0.9 V
XI input osc clock common mode VDDIO 3V3 1.65 V
Rseries Integrated MAC Series Termination Resistor RX_D[3:0], RX_ER, RX_DV, RX_CLK, TX_CLK 50 Ω
(1) Ensured by production test, characterization or design
(2) Requires register 0x030E to program to 0x4A40