SNLS484G February 2015 – October 2022 DP83867CR , DP83867IR
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
If an external clock source is used, XO should be left floating. For a 1.8-V clock source, XI should be tied to the clock source. For a 3.3-V or 2.5-V clock source, a capacitor divider is recommended as shown in Figure 9-3. For a 3.3-V clock source, the CD1 and CD2 capacitors used are recommended to be 27 pF. If a 2.5-V clock source is used check with the vendor for recommended capacitor loads. The values of CD1 and CD2 shall be adjusted to meet XI Input pin specification defined in Section 7.5.
The CMOS 25-MHz oscillator specifications are listed in Table 9-2. Additionally, the maximum oscillator phase noise tolerated by the PHY is shown in Figure 9-4
PARAMETER | TEST CONDITION | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Frequency | 25 | MHz | |||
Frequency Tolerance | Operational Temperature | ±50 | ppm | ||
Frequency Stability | 1 year aging | ±50 | ppm | ||
Rise / Fall Time | 20% - 80% | 5 | ns | ||
Symmetry | Duty Cycle | 40% | 60% | ||
Jitter RMS | Integration Band: 12 kHz to 5 MHz | 11 | ps |