SNLS614A September 2018 – December 2018 DP83869HM
When the RGMII interface is operating in the 100-Mbps mode, the RGMII clock rate is reduced to 25 MHz. For 10-Mbps operation, the clock is further reduced to 2.5 MHz. In the RGMII 10/100 mode, the transmit clock RGMII TX_CLK is generated by the MAC and the receive clock RGMII RX_CLK is generated by the PHY. During the packet receiving operation, the RGMII RX_CLK may be stretched on either the positive or negative pulse to accommodate the transition from the free-running clock to a data synchronous clock domain. When the speed of the PHY changes, a similar stretching of the positive or negative pulses is allowed. No glitch is allowed on the clock signals during clock speed transitions.
This interface operates at 10- and 100-Mbps speeds the same way it does at 1000-Mbps mode with the exception that the data may be duplicated on the falling edge of the appropriate clock.
The MAC holds the RGMII TX_CLK low until it has ensured that it is operating at the same speed as the PHY.