SNLS614A September 2018 – December 2018 DP83869HM
All RGMII signals are positive logic. The 8-bit data is multiplexed by taking advantage of both clock edges. The lower 4 bits are latched on the positive clock edge and the upper 4 bits are latched on trailing clock edge. The control signals are multiplexed into a single clock cycle using the same technique.
To reduce power consumption of RGMII interface, (TX_EN - TX_ERR) and (RX_DV - RX_ERR) are encoded in a manner that minimizes transitions during normal network operation. TX_CTRL pin will denote TX_EN on rising edge of GTX_CLK and will denote a logic derivative of TX_EN and TX_ERR on the falling edge of GTX_CLK. RX_CTRL will denote RX_DV on rising edge of RX_CLK and will denote a logic derivative of RX_DV and RX_ERR on the falling edge of RX_CLK. The encoding for the TX_ERR and RX_ERR is given in Equation 1 and Equation 2:
When receiving a valid frame with no error, RX_CTRL = True is generated as a logic high on the rising edge of RX_CLK and RX_CTRL = False is generated as a logic high at the falling edge of RX_CLK. When no frame is being received, RX_CTRL = False is generated as a logic low on the rising edge of RX_CLK and RX_CTRL = False is generated as a logic low on the falling edge of RX_CLK.
The TX_CTRL is treated in a similar manner. During normal frame transmission, the signal stays at a logic high for both edges of GTX_CLK and during the period between frames where no error is indicated, the signal stays low for both edges.