9.6.1.21 BIST_CONTROL Register (Address = 0x16) [reset = 0x0]
BIST_CONTROL is shown in Figure 53 and described in Table 41.
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This register is used for Build-In Self Test (BIST) configuration. The BIST functionality provides Pseudo Random Bit Stream (PRBS) mechanism including packet generation generator and checker. Selection of the exact loopback point in the signal chain is also done in this register.
Figure 53. BIST_CONTROL Register
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
PACKET_GEN_EN_3:0 |
RESERVED |
RESERVED |
RESERVED |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
R/W-0x0 |
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
REV_LOOP_RX_DATA_CTRL |
MII_LOOP_TX_DATA_CTRL |
LOOP_TX_DATA_MIX |
LOOPBACK_MODE |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 41. BIST_CONTROL Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
15-12 |
PACKET_GEN_EN_3:0 |
R/W |
0x0 |
These bits along controls PRBS generator.Other values are not applicable.
0x0 = Disable PRBS
0xF = Enable Continuous PRBS
|
11-10 |
RESERVED |
R |
0x0 |
Reserved
|
9 |
RESERVED |
R/W |
0x0 |
Reserved
|
8 |
RESERVED |
R/W |
0x0 |
Reserved
|
7 |
REV_LOOP_RX_DATA_CTRL |
R/W |
0x0 |
Reverse Loopback Receive Data Control: This bit may only be set in Reverse Loopback mode
0x0 = Suppress RX packets to MAC in reverse loop
0x1 = Send RX packets to MAC in reverse loop
|
6 |
MII_LOOP_TX_DATA_CTRL |
R/W |
0x0 |
MII Loopback Transmit Data Control: This bit may only be set in MII Loopback mode
0x0 = Suppress data to MDI in MII loop
0x1 = Transmit data to MDI in MII loop
|
5-2 |
LOOP_TX_DATA_MIX |
R/W |
0x0 |
Loopback Mode Select: PCS loopback must be disabled (Bits[1:0] = 00)
0x0 = No Loopback
0x1 = Digital Loopback
0x2 = Analog Loopback
0x4 = External Loopback
0x8 = Reverse Loopback
|
1-0 |
LOOPBACK_MODE |
R/W |
0x0 |
PCS Loopback Select When configured in 1000Base-T x1b = Loop before 1000Base-T signal processing. When configured in 100Base-TX
0x0 = See bits [5:2] 01b = Loop before scrambler 10b = Loop after scrambler, before MLT3 encoder 11b = Loop after MLT3 encoder
|