DP83869HM datasheet

SNLS614A September 2018 – December 2018 DP83869HM

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

RGZ|48
- MPQF123F

Thermal pad, mechanical data (Package|Pins)

Orderable Information

9.6.1 DP83869 Registers

Table 19 lists the memory-mapped registers for the DP83869 registers. All register offset addresses not listed in Table 19 should be considered as reserved locations and the register contents should not be modified.

Table 19. DP83869 Registers

Address	Acronym	Register Name	Section
0x0	BMCR	Basic Mode Control Register	Go
0x1	BMSR	Basic Mode Status Register	Go
0x2	PHYIDR1	PHY Identifier Register #1	Go
0x3	PHYIDR2	PHY Identifier Register #2	Go
0x4	ANAR	Auto-Negotiation Advertisement Register	Go
0x5	ALNPAR	Auto-Negotiation Link Partner Ability Register	Go
0x6	ANER	Auto-Negotiate Expansion Register	Go
0x7	ANNPTR	Auto-Negotiation Next Page Transmit Register	Go
0x8	ANLNPTR	Auto-Negotiation Link Partner Next Page Receive Register	Go
0x9	GEN_CFG1	Configuration Register 1	Go
0xA	GEN_STATUS1	Status Register 1	Go
0xD	REGCR	Register Control Register	Go
0xE	ADDAR	Address or Data Register	Go
0xF	1KSCR	1000BASE-T Status Register	Go
0x10	PHY_CONTROL	PHY Control Register	Go
0x11	PHY_STATUS	PHY Status Register	Go
0x12	INTERRUPT_MASK	MII Interrupt Control Register	Go
0x13	INTERRUPT_STATUS	Interrupt Status Register	Go
0x14	GEN_CFG2	Configuration Register 2	Go
0x15	RX_ERR_CNT		Go
0x16	BIST_CONTROL	BIST Control Register	Go
0x17	GEN_STATUS2	Status Register 2	Go
0x18	LEDS_CFG1	LED Configuration Register 1	Go
0x19	LEDS_CFG2	LED Configuration Register 2	Go
0x1A	LEDS_CFG3	LED Configuration Register 3	Go
0x1E	GEN_CFG4	Configuration Register 3	Go
0x1F	GEN_CTRL	Control Register	Go
0x25	ANALOG_TEST_CTRL	Testmode Channel Control Register	Go
0x2C	GEN_CFG_ENH_AMIX		Go
0x2D	GEN_CFG_FLD		Go
0x2E	GEN_CFG_FLD_THR		Go
0x31	GEN_CFG3	Configuration Register 4	Go
0x32	RGMII_CTRL	RGMII Control Register	Go
0x33	RGMII_CTRL2		Go
0x37	SGMII_AUTO_NEG_STATUS	SGMII Autonegotiation Status Register	Go
0x39	PRBS_TX_CHK_CTRL		Go
0x3A	PRBS_TX_CHK_BYTE_CNT		Go
0x43	G_100BT_REG0		Go
0x4F	SERDES_SYNC_STS		Go
0x6E	STRAP_STS	Strap Status Register	Go
0x86	ANA_RGMII_DLL_CTRL	RGMII Delay Control Register	Go
0x134	RXF_CFG		Go
0x135	RXF_STATUS		Go
0x170	IO_MUX_CFG		Go
0x180	TDR_GEN_CFG1		Go
0x181	TDR_GEN_CFG2		Go
0x182	TDR_SEG_DURATION1		Go
0x183	TDR_SEG_DURATION2		Go
0x184	TDR_GEN_CFG3		Go
0x185	TDR_GEN_CFG4		Go
0x190	TDR_PEAKS_LOC_A_0_1		Go
0x191	TDR_PEAKS_LOC_A_2_3		Go
0x192	TDR_PEAKS_LOC_A_4_B_0		Go
0x193	TDR_PEAKS_LOC_B_1_2		Go
0x194	TDR_PEAKS_LOC_B_3_4		Go
0x195	TDR_PEAKS_LOC_C_0_1		Go
0x196	TDR_PEAKS_LOC_C_2_3		Go
0x197	TDR_PEAKS_LOC_C_4_D_0		Go
0x198	TDR_PEAKS_LOC_D_1_2		Go
0x199	TDR_PEAKS_LOC_D_3_4		Go
0x1A4	TDR_GEN_STATUS		Go
0x1A5	TDR_PEAKS_SIGN_A_B		Go
0x1A6	TDR_PEAKS_SIGN_C_D		Go
0x1DF	OP_MODE_DECODE		Go
0x1E0	GPIO_MUX_CTRL		Go
0xC00	FX_CTRL	Fiber Control Register	Go
0xC01	FX_STS	Fiber Status Register	Go
0xC02	FX_PHYID1	Fiber PHYID Register 1	Go
0xC03	FX_PHYID2	Fiber PHYID Register 2	Go
0xC04	FX_ANADV	Fiber Autonegotiation Advertisement Register	Go
0xC05	FX_LPABL	Fiber Link Partner Ability Register	Go
0xC06	FX_ANEXP	Fiber Autonegotiation Expansion Register	Go
0xC07	FX_LOCNP	Fiber LOC Next Page Register	Go
0xC08	FX_LPNP	Fiber Link Partner Next Page Register	Go
0xC18	FX_INT_EN	Fiber Interrupt Enable Register	Go
0xC19	FX_INT_STS	Fiber Interrupt Status Register	Go

Complex bit access types are encoded to fit into small table cells. Table 20 shows the codes that are used for access types in this section.

Table 20. DP83869 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
RC	C R	to Clear Read
RH	H R	Set or cleared by hardware Read
Write Type
W	W	Write
W1C	1C W	1 to clear Write
WoP	W	Write
WtoP	W	Write
Reset or Default Value
-n		Value after reset or the default value