9.6.1.38 G_100BT_REG0 Register (Address = 0x43) [reset = 0x7A0]
G_100BT_REG0 is shown in Figure 70 and described in Table 58.
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Figure 70. G_100BT_REG0 Register
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
RESERVED |
RESERVED |
RESERVED |
R-0x0 |
R/W-0x0 |
R/W-0xF |
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
RESERVED |
RESERVED |
RESERVED |
RESERVED |
RESERVED |
RESERVED |
FAST_RX_DV |
R/W-0xF |
R/W-0x0 |
R/W-0x1 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
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Table 58. G_100BT_REG0 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
15-12 |
RESERVED |
R |
0x0 |
Reserved
|
11 |
RESERVED |
R/W |
0x0 |
Reserved
|
10-7 |
RESERVED |
R/W |
0xF |
Reserved
|
6 |
RESERVED |
R/W |
0x0 |
Reserved
|
5 |
RESERVED |
R/W |
0x1 |
Reserved
|
4 |
RESERVED |
R/W |
0x0 |
Reserved
|
3 |
RESERVED |
R/W |
0x0 |
Reserved
|
2 |
RESERVED |
R/W |
0x0 |
Reserved
|
1 |
RESERVED |
R/W |
0x0 |
Reserved
|
0 |
FAST_RX_DV |
R/W |
0x0 |
Enable Fast RX_DV for low latency in 100Mbps mode.
0x0 = Fast rx dv disable
0x1 = Fast rx dv enable
|