15 |
RESERVED |
R/W |
0x0 |
Reserved
|
14 |
CFG_FAST_ANEG_EN |
R/W |
0x0 |
Enable Fast ANEG mode
|
13-12 |
CFG_FAST_ANEG_SEL_VAL |
R/W |
0x0 |
when Fast ANEG mode enabled, value will select short timer duration 0x0 will be the shortest timers config and 0x2 the longest
|
11 |
CFG_ANEG_ADV_FD_EN |
R/W |
0x0 |
this but enables to declare FD also in parallel detect link, the IEEE defien on parallel detect to always declare HD, this bit allows also to declare FD in this scenario
|
10 |
RESTART_STATUS_BITS_EN |
R/W |
0x0 |
reset enable 1b = clear all the phy status bits (part of register 0x11) 0b = do not clear the status bit
|
9 |
CFG_ROBUST_AMDIX_EN |
R/W |
0x0 |
Enable Robust Auto MDI/MDIX resolution
|
8 |
CFG_FAST_AMDIX_EN |
R/W |
0x0 |
Enabe Fast Auto MDI-X mode
|
7 |
INT_OE |
R/W |
0x0 |
Interrupt Output Enable: 1b = INTN/PWDNN Pad is an Interrupt Output 0b = INTN/PWDNN Pad in an Power Down Input
|
6 |
FORCE_INTERRUPT |
R/W |
0x0 |
1b = Assert interrupt pin 0b = Normal interrupt mode
|
5 |
RESERVED |
R/W |
0x0 |
Reserved
|
4 |
RESERVED |
R/W |
0x1 |
Reserved
|
3 |
FORCE_1G_AUTONEG_EN |
R/W |
0x0 |
1b = Invoke Auto-Negotiation with only 1G advertised when manual speed in register 0 is 1G 0b = Do not invoke Auto-Negotiation when manual speed in register 0 is 1G
|
2 |
TDR_FAIL |
R |
0x0 |
|
1 |
TDR_DONE |
R |
0x1 |
|
0 |
TDR_START |
RH/WtoP |
0x0 |
1b = Start TDR 0b = TDR Completed
|