SNLS614A September 2018 – December 2018 DP83869HM
PRODUCTION DATA.
INTERRUPT_MASK is shown in Figure 49 and described in Table 37.
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This register implements the Interrupt PHY Specific Control register. The individual interrupt events must be enabled by setting bits in the MII Interrupt Control Register (MICR). If the corresponding enable bit in the register is set, an interrupt is generated if the event occurs.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
AUTONEG_ERR_INT_EN | SPEED_CHNG_INT_EN | DUPLEX_MODE_CHNG_INT_EN | PAGE_RECEIVED_INT_EN | AUTONEG_COMP_INT_EN | LINK_STATUS_CHNG_INT_EN | EEE_ERR_INT_EN | FALSE_CARRIER_INT_EN |
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ADC_FIFO_OVF_UNF_INT_EN | MDI_CROSSOVER_CHNG_INT_EN | SPEED_OPT_EVENT_INT_EN | SLEEP_MODE_CHNG_INT_EN | WOL_INT_EN | XGMII_ERR_INT_EN | POLARITY_CHNG_INT_EN | JABBER_INT_EN |
R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 |