SNLS614A September   2018  – December 2018 DP83869HM

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Standard Ethernet System Block Diagram
  4. Revision History
  5. Description (continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     RGZ Package (VQFN) Pin Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  WoL (Wake-on-LAN) Packet Detection
        1. 9.3.1.1 Magic Packet Structure
        2. 9.3.1.2 Magic Packet Example
        3. 9.3.1.3 Wake-on-LAN Configuration and Status
      2. 9.3.2  Start of Frame Detect for IEEE 1588 Time Stamp
        1. 9.3.2.1 SFD Latency Variation and Determinism
          1. 9.3.2.1.1 1000-Mb SFD Variation in Master Mode
          2. 9.3.2.1.2 1000-Mb SFD Variation in Slave Mode
          3. 9.3.2.1.3 100-Mb SFD Variation
      3. 9.3.3  Clock Output
      4. 9.3.4  Loopback Mode
        1. 9.3.4.1 Near-End Loopback
          1. 9.3.4.1.1 MII Loopback
          2. 9.3.4.1.2 PCS Loopback
          3. 9.3.4.1.3 Digital Loopback
          4. 9.3.4.1.4 Analog Loopback
          5. 9.3.4.1.5 External Loopback
          6. 9.3.4.1.6 Far-End (Reverse) Loopback
      5. 9.3.5  BIST Configuration
      6. 9.3.6  Interrupt
      7. 9.3.7  Power-Saving Modes
        1. 9.3.7.1 IEEE Power Down
        2. 9.3.7.2 Active Sleep
        3. 9.3.7.3 Passive Sleep
      8. 9.3.8  Mirror Mode
      9. 9.3.9  Speed Optimization
      10. 9.3.10 Cable Diagnostics
        1. 9.3.10.1 TDR
      11. 9.3.11 Fast Link Drop
      12. 9.3.12 Jumbo Frames
    4. 9.4 Device Functional Modes
      1. 9.4.1  Copper Ethernet
        1. 9.4.1.1 1000BASE-T
        2. 9.4.1.2 100BASE-TX
        3. 9.4.1.3 10BASE-Te
      2. 9.4.2  Fiber Ethernet
        1. 9.4.2.1 1000BASE-X
        2. 9.4.2.2 100BASE-FX
      3. 9.4.3  Serial GMII (SGMII)
      4. 9.4.4  Reduced GMII (RGMII)
        1. 9.4.4.1 1000-Mbps Mode Operation
        2. 9.4.4.2 1000-Mbps Mode Timing
        3. 9.4.4.3 10- and 100-Mbps Mode
      5. 9.4.5  Media Independent Interface (MII)
      6. 9.4.6  Bridge Modes
        1. 9.4.6.1 RGMII-to-SGMII Mode
        2. 9.4.6.2 SGMII-to-RGMII Mode
      7. 9.4.7  Media Convertor Mode
      8. 9.4.8  Register Configuration for Operational Modes
        1. 9.4.8.1 RGMII-to-Copper Ethernet Mode
        2. 9.4.8.2 RGMII-to-1000Base-X Mode
        3. 9.4.8.3 RGMII-to-SGMII Bridge Mode
        4. 9.4.8.4 1000M Media Convertor Mode
        5. 9.4.8.5 100M Media Convertor Mode
        6. 9.4.8.6 SGMII-to-Copper Ethernet Mode
      9. 9.4.9  Serial Management Interface
        1. 9.4.9.1 Extended Address Space Access
          1. 9.4.9.1.1 Write Address Operation
          2. 9.4.9.1.2 Read Address Operation
          3. 9.4.9.1.3 Write (No Post Increment) Operation
          4. 9.4.9.1.4 Read (No Post Increment) Operation
          5. 9.4.9.1.5 Write (Post Increment) Operation
          6. 9.4.9.1.6 Read (Post Increment) Operation
          7. 9.4.9.1.7 Example of Read Operation Using Indirect Register Access
          8. 9.4.9.1.8 Example of Write Operation Using Indirect Register Access
      10. 9.4.10 Auto-Negotiation
        1. 9.4.10.1 Speed and Duplex Selection - Priority Resolution
        2. 9.4.10.2 Master and Slave Resolution
        3. 9.4.10.3 Pause and Asymmetrical Pause Resolution
        4. 9.4.10.4 Next Page Support
        5. 9.4.10.5 Parallel Detection
        6. 9.4.10.6 Restart Auto-Negotiation
        7. 9.4.10.7 Enabling Auto-Negotiation Through Software
        8. 9.4.10.8 Auto-Negotiation Complete Time
        9. 9.4.10.9 Auto-MDIX Resolution
    5. 9.5 Programming
      1. 9.5.1 Strap Configuration
        1. 9.5.1.1 Straps for PHY Address
        2. 9.5.1.2 Strap for DP83869HM Functional Mode Selection
        3. 9.5.1.3 Straps for RGMII/SGMII to Copper
        4. 9.5.1.4 Straps for RGMII to 1000Base-X
        5. 9.5.1.5 Straps for RGMII to 100Base-FX
        6. 9.5.1.6 Straps for Bridge Mode (SGMII-RGMII)
        7. 9.5.1.7 Straps for 100M Media Convertor
        8. 9.5.1.8 Straps for 1000M Media Convertor
      2. 9.5.2 LED Configuration
      3. 9.5.3 Reset Operation
        1. 9.5.3.1 Hardware Reset
        2. 9.5.3.2 IEEE Software Reset
        3. 9.5.3.3 Global Software Reset
        4. 9.5.3.4 Global Software Restart
    6. 9.6 Register Maps
      1. 9.6.1 DP83869 Registers
        1. 9.6.1.1  BMCR Register (Address = 0x0) [reset = 0x1140]
          1. Table 21. BMCR Register Field Descriptions
        2. 9.6.1.2  BMSR Register (Address = 0x1) [reset = 0x7949]
          1. Table 22. BMSR Register Field Descriptions
        3. 9.6.1.3  PHYIDR1 Register (Address = 0x2) [reset = 0x2000]
          1. Table 23. PHYIDR1 Register Field Descriptions
        4. 9.6.1.4  PHYIDR2 Register (Address = 0x3) [reset = 0xA0F1]
          1. Table 24. PHYIDR2 Register Field Descriptions
        5. 9.6.1.5  ANAR Register (Address = 0x4) [reset = 0x1]
          1. Table 25. ANAR Register Field Descriptions
        6. 9.6.1.6  ALNPAR Register (Address = 0x5) [reset = 0x0]
          1. Table 26. ALNPAR Register Field Descriptions
        7. 9.6.1.7  ANER Register (Address = 0x6) [reset = 0x64]
          1. Table 27. ANER Register Field Descriptions
        8. 9.6.1.8  ANNPTR Register (Address = 0x7) [reset = 0x2001]
          1. Table 28. ANNPTR Register Field Descriptions
        9. 9.6.1.9  ANLNPTR Register (Address = 0x8) [reset = 0x2001]
          1. Table 29. ANLNPTR Register Field Descriptions
        10. 9.6.1.10 GEN_CFG1 Register (Address = 0x9) [reset = 0x300]
          1. Table 30. GEN_CFG1 Register Field Descriptions
        11. 9.6.1.11 GEN_STATUS1 Register (Address = 0xA) [reset = 0x0]
          1. Table 31. GEN_STATUS1 Register Field Descriptions
        12. 9.6.1.12 REGCR Register (Address = 0xD) [reset = 0x0]
          1. Table 32. REGCR Register Field Descriptions
        13. 9.6.1.13 ADDAR Register (Address = 0xE) [reset = 0x0]
          1. Table 33. ADDAR Register Field Descriptions
        14. 9.6.1.14 1KSCR Register (Address = 0xF) [reset = 0xF000]
          1. Table 34. 1KSCR Register Field Descriptions
        15. 9.6.1.15 PHY_CONTROL Register (Address = 0x10) [reset = 0x5048]
          1. Table 35. PHY_CONTROL Register Field Descriptions
        16. 9.6.1.16 PHY_STATUS Register (Address = 0x11) [reset = 0x0]
          1. Table 36. PHY_STATUS Register Field Descriptions
        17. 9.6.1.17 INTERRUPT_MASK Register (Address = 0x12) [reset = 0x0]
          1. Table 37. INTERRUPT_MASK Register Field Descriptions
        18. 9.6.1.18 INTERRUPT_STATUS Register (Address = 0x13) [reset = 0x0]
          1. Table 38. INTERRUPT_STATUS Register Field Descriptions
        19. 9.6.1.19 GEN_CFG2 Register (Address = 0x14) [reset = 0x29C7]
          1. Table 39. GEN_CFG2 Register Field Descriptions
        20. 9.6.1.20 RX_ERR_CNT Register (Address = 0x15) [reset = 0x0]
          1. Table 40. RX_ERR_CNT Register Field Descriptions
        21. 9.6.1.21 BIST_CONTROL Register (Address = 0x16) [reset = 0x0]
          1. Table 41. BIST_CONTROL Register Field Descriptions
        22. 9.6.1.22 GEN_STATUS2 Register (Address = 0x17) [reset = 0x40]
          1. Table 42. GEN_STATUS2 Register Field Descriptions
        23. 9.6.1.23 LEDS_CFG1 Register (Address = 0x18) [reset = 0x6150]
          1. Table 43. LEDS_CFG1 Register Field Descriptions
        24. 9.6.1.24 LEDS_CFG2 Register (Address = 0x19) [reset = 0x4444]
          1. Table 44. LEDS_CFG2 Register Field Descriptions
        25. 9.6.1.25 LEDS_CFG3 Register (Address = 0x1A) [reset = 0x2]
          1. Table 45. LEDS_CFG3 Register Field Descriptions
        26. 9.6.1.26 GEN_CFG4 Register (Address = 0x1E) [reset = 0x12]
          1. Table 46. GEN_CFG4 Register Field Descriptions
        27. 9.6.1.27 GEN_CTRL Register (Address = 0x1F) [reset = 0x0]
          1. Table 47. GEN_CTRL Register Field Descriptions
        28. 9.6.1.28 ANALOG_TEST_CTRL Register (Address = 0x25) [reset = 0x480]
          1. Table 48. ANALOG_TEST_CTRL Register Field Descriptions
        29. 9.6.1.29 GEN_CFG_ENH_AMIX Register (Address = 0x2C) [reset = 0x141F]
          1. Table 49. GEN_CFG_ENH_AMIX Register Field Descriptions
        30. 9.6.1.30 GEN_CFG_FLD Register (Address = 0x2D) [reset = 0x0]
          1. Table 50. GEN_CFG_FLD Register Field Descriptions
        31. 9.6.1.31 GEN_CFG_FLD_THR Register (Address = 0x2E) [reset = 0x221]
          1. Table 51. GEN_CFG_FLD_THR Register Field Descriptions
        32. 9.6.1.32 GEN_CFG3 Register (Address = 0x31) [reset = 0x10B0]
          1. Table 52. GEN_CFG3 Register Field Descriptions
        33. 9.6.1.33 RGMII_CTRL Register (Address = 0x32) [reset = 0xD0]
          1. Table 53. RGMII_CTRL Register Field Descriptions
        34. 9.6.1.34 RGMII_CTRL2 Register (Address = 0x33) [reset = 0x0]
          1. Table 54. RGMII_CTRL2 Register Field Descriptions
        35. 9.6.1.35 SGMII_AUTO_NEG_STATUS Register (Address = 0x37) [reset = 0x0]
          1. Table 55. SGMII_AUTO_NEG_STATUS Register Field Descriptions
        36. 9.6.1.36 PRBS_TX_CHK_CTRL Register (Address = 0x39) [reset = 0x0]
          1. Table 56. PRBS_TX_CHK_CTRL Register Field Descriptions
        37. 9.6.1.37 PRBS_TX_CHK_BYTE_CNT Register (Address = 0x3A) [reset = 0x0]
          1. Table 57. PRBS_TX_CHK_BYTE_CNT Register Field Descriptions
        38. 9.6.1.38 G_100BT_REG0 Register (Address = 0x43) [reset = 0x7A0]
          1. Table 58. G_100BT_REG0 Register Field Descriptions
        39. 9.6.1.39 SERDES_SYNC_STS Register (Address = 0x4F) [reset = 0x0]
          1. Table 59. SERDES_SYNC_STS Register Field Descriptions
        40. 9.6.1.40 STRAP_STS Register (Address = 0x6E) [reset = 0x0]
          1. Table 60. STRAP_STS Register Field Descriptions
        41. 9.6.1.41 ANA_RGMII_DLL_CTRL Register (Address = 0x86) [reset = 0x77]
          1. Table 61. ANA_RGMII_DLL_CTRL Register Field Descriptions
        42. 9.6.1.42 RXF_CFG Register (Address = 0x134) [reset = 0x1000]
          1. Table 62. RXF_CFG Register Field Descriptions
        43. 9.6.1.43 RXF_STATUS Register (Address = 0x135) [reset = 0x0]
          1. Table 63. RXF_STATUS Register Field Descriptions
        44. 9.6.1.44 IO_MUX_CFG Register (Address = 0x170) [reset = X]
          1. Table 64. IO_MUX_CFG Register Field Descriptions
        45. 9.6.1.45 TDR_GEN_CFG1 Register (Address = 0x180) [reset = 0x752]
          1. Table 65. TDR_GEN_CFG1 Register Field Descriptions
        46. 9.6.1.46 TDR_GEN_CFG2 Register (Address = 0x181) [reset = 0xC850]
          1. Table 66. TDR_GEN_CFG2 Register Field Descriptions
        47. 9.6.1.47 TDR_SEG_DURATION1 Register (Address = 0x182) [reset = 0x5326]
          1. Table 67. TDR_SEG_DURATION1 Register Field Descriptions
        48. 9.6.1.48 TDR_SEG_DURATION2 Register (Address = 0x183) [reset = 0xA01E]
          1. Table 68. TDR_SEG_DURATION2 Register Field Descriptions
        49. 9.6.1.49 TDR_GEN_CFG3 Register (Address = 0x184) [reset = 0xE976]
          1. Table 69. TDR_GEN_CFG3 Register Field Descriptions
        50. 9.6.1.50 TDR_GEN_CFG4 Register (Address = 0x185) [reset = 0x19CF]
          1. Table 70. TDR_GEN_CFG4 Register Field Descriptions
        51. 9.6.1.51 TDR_PEAKS_LOC_A_0_1 Register (Address = 0x190) [reset = 0x0]
          1. Table 71. TDR_PEAKS_LOC_A_0_1 Register Field Descriptions
        52. 9.6.1.52 TDR_PEAKS_LOC_A_2_3 Register (Address = 0x191) [reset = 0x0]
          1. Table 72. TDR_PEAKS_LOC_A_2_3 Register Field Descriptions
        53. 9.6.1.53 TDR_PEAKS_LOC_A_4_B_0 Register (Address = 0x192) [reset = 0x0]
          1. Table 73. TDR_PEAKS_LOC_A_4_B_0 Register Field Descriptions
        54. 9.6.1.54 TDR_PEAKS_LOC_B_1_2 Register (Address = 0x193) [reset = 0x0]
          1. Table 74. TDR_PEAKS_LOC_B_1_2 Register Field Descriptions
        55. 9.6.1.55 TDR_PEAKS_LOC_B_3_4 Register (Address = 0x194) [reset = 0x0]
          1. Table 75. TDR_PEAKS_LOC_B_3_4 Register Field Descriptions
        56. 9.6.1.56 TDR_PEAKS_LOC_C_0_1 Register (Address = 0x195) [reset = 0x0]
          1. Table 76. TDR_PEAKS_LOC_C_0_1 Register Field Descriptions
        57. 9.6.1.57 TDR_PEAKS_LOC_C_2_3 Register (Address = 0x196) [reset = 0x0]
          1. Table 77. TDR_PEAKS_LOC_C_2_3 Register Field Descriptions
        58. 9.6.1.58 TDR_PEAKS_LOC_C_4_D_0 Register (Address = 0x197) [reset = 0x0]
          1. Table 78. TDR_PEAKS_LOC_C_4_D_0 Register Field Descriptions
        59. 9.6.1.59 TDR_PEAKS_LOC_D_1_2 Register (Address = 0x198) [reset = 0x0]
          1. Table 79. TDR_PEAKS_LOC_D_1_2 Register Field Descriptions
        60. 9.6.1.60 TDR_PEAKS_LOC_D_3_4 Register (Address = 0x199) [reset = 0x0]
          1. Table 80. TDR_PEAKS_LOC_D_3_4 Register Field Descriptions
        61. 9.6.1.61 TDR_GEN_STATUS Register (Address = 0x1A4) [reset = 0x0]
          1. Table 81. TDR_GEN_STATUS Register Field Descriptions
        62. 9.6.1.62 TDR_PEAKS_SIGN_A_B Register (Address = 0x1A5) [reset = 0x0]
          1. Table 82. TDR_PEAKS_SIGN_A_B Register Field Descriptions
        63. 9.6.1.63 TDR_PEAKS_SIGN_C_D Register (Address = 0x1A6) [reset = 0x0]
          1. Table 83. TDR_PEAKS_SIGN_C_D Register Field Descriptions
        64. 9.6.1.64 OP_MODE_DECODE Register (Address = 0x1DF) [reset = 0x40]
          1. Table 84. OP_MODE_DECODE Register Field Descriptions
        65. 9.6.1.65 GPIO_MUX_CTRL Register (Address = 0x1E0) [reset = 0x417A]
          1. Table 85. GPIO_MUX_CTRL Register Field Descriptions
        66. 9.6.1.66 FX_CTRL Register (Address = 0xC00) [reset = 0x1140]
          1. Table 86. FX_CTRL Register Field Descriptions
        67. 9.6.1.67 FX_STS Register (Address = 0xC01) [reset = 0x6149]
          1. Table 87. FX_STS Register Field Descriptions
        68. 9.6.1.68 FX_PHYID1 Register (Address = 0xC02) [reset = 0x2000]
          1. Table 88. FX_PHYID1 Register Field Descriptions
        69. 9.6.1.69 FX_PHYID2 Register (Address = 0xC03) [reset = 0xA0F1]
          1. Table 89. FX_PHYID2 Register Field Descriptions
        70. 9.6.1.70 FX_ANADV Register (Address = 0xC04) [reset = 0x20]
          1. Table 90. FX_ANADV Register Field Descriptions
        71. 9.6.1.71 FX_LPABL Register (Address = 0xC05) [reset = 0x0]
          1. Table 91. FX_LPABL Register Field Descriptions
        72. 9.6.1.72 FX_ANEXP Register (Address = 0xC06) [reset = 0x0]
          1. Table 92. FX_ANEXP Register Field Descriptions
        73. 9.6.1.73 FX_LOCNP Register (Address = 0xC07) [reset = 0x2001]
          1. Table 93. FX_LOCNP Register Field Descriptions
        74. 9.6.1.74 FX_LPNP Register (Address = 0xC08) [reset = 0x0]
          1. Table 94. FX_LPNP Register Field Descriptions
        75. 9.6.1.75 FX_INT_EN Register (Address = 0xC18) [reset = 0x3FF]
          1. Table 95. FX_INT_EN Register Field Descriptions
        76. 9.6.1.76 FX_INT_STS Register (Address = 0xC19) [reset = 0x0]
          1. Table 96. FX_INT_STS Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Copper Ethernet Typical Application
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Clock Input
            1. 10.2.1.2.1.1 Crystal Recommendations
            2. 10.2.1.2.1.2 External Clock Source Recommendation
          2. 10.2.1.2.2 Magnetics Requirements
            1. 10.2.1.2.2.1 Magnetics Connection
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Fiber Ethernet Typical Ethernet
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Transceiver Connections
        3. 10.2.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Two Supply Configuration
    2. 11.2 Three Supply Configuration
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Signal Traces
        1. 12.1.1.1 MAC Interface Layout Guidelines
          1. 12.1.1.1.1 SGMII Layout Guidelines
          2. 12.1.1.1.2 RGMII Layout Guidelines
        2. 12.1.1.2 MDI Layout Guidelines
      2. 12.1.2 Return Path
      3. 12.1.3 Transformer Layout
      4. 12.1.4 Metal Pour
      5. 12.1.5 PCB Layer Stacking
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

RGZ Package
(48-Pin VQFN)
Top View
DP83869HM DP83869pinout.gif

RGZ Package (VQFN) Pin Functions

PIN I/O TYPE DESCRIPTION
NO. NAME
1 TD_P_A I/O Analog Differential Transmit and Receive Signals
2 TD_M_A I/O Analog Differential Transmit and Receive Signals
3 VDDA2P5 I Power 2.5-V Analog Supply (+/-5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND.
4 TD_P_B I/O Analog Differential Transmit and Receive Signals
5 TD_M_B I/O Analog Differential Transmit and Receive Signals
6 VDD1P1 I Power 1.1-V Analog Supply (+/-10%). Each pin requires a 1-µF and 0.1-µF capacitor to GND.
7 TD_P_C I/O Analog Differential Transmit and Receive Signals
8 TD_M_C I/O Analog Differential Transmit and Receive Signals
9 VDDA2P5 I Power 2.5-V Analog Supply (+/-5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND.
10 TD_P_D I/O Analog Differential Transmit and Receive Signals
11 TD_M_D I/O Analog Differential Transmit and Receive Signals
12 RBIAS I Bias Resistor Connection. An 11-kΩ ±1% resistor should be connected from RBIAS to GND.
13 VDDA1P8_1 I Power No external supply is required for this pin in two-supply mode. When unused, no connections should be made to these pins. In three-supply mode, an external 1.8-V(±5%) supply can be connected to these pins. When using an external supply, each pin requires a 1-µF and 0.1-µF capacitor to GND.
14 SON O Analog Differential SGMII or Fiber Data Output: This signal carries data from the PHY to the MAC, fiber transceiver, or link partner in SGMII and fiber modes. This pin should be AC-coupled to the distant device through a 0.1-µF capacitor. This pin provides LVDS signals, additional components may be required for the optical transceiver.
15 SOP O Analog Differential SGMII or Fiber Data Output: This signal carries data from the PHY to the MAC, fiber transceiver, or link partner in SGMII and fiber modes. This pin should be AC-coupled to the distant device through a 0.1-µF capacitor. This pin provides LVDS signals, additional components may be required for the optical transceiver
16 SIP I Analog Differential SGMII or Fiber Data Input: This signal carries data from the MAC, fiber transceiver, or link partner, to the PHY in SGMII and fiber modes. This pin should be AC-coupled to the distant device through a 0.1-µF capacitor. This pin accepts LVDS signals, additional components may be required for the optical transceiver
17 SIN I Analog Differential SGMII or Fiber Data Input: This signal carries data from the MAC, fiber transceiver, or link partner, to the PHY in SGMII and fiber modes. This pin should be AC-coupled to the distant device through a 0.1-µF capacitor. This pin accepts LVDS signals, additional components may be required for the optical transceiver
18 VDDIO I Power I/O Power: 1.8V (±5%), 2.5V (±5%) or 3.3V (±5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND
19 XO O Clock CRYSTAL OSCILLATOR OUTPUT: Second terminal for 25-MHz crystal. Must be left floating if a clock oscillator is used.
20 XI I Clock CRYSTAL OSCILLATOR INPUT: 25-MHz oscillator or crystal input.
21 JTAG_CLK/TX_ER I WPU JTAG TEST CLOCK: IEEE 1149.1 Test Clock input, primary clock source for all test logic input and output controlled by the testing entity.
MII Mode: In MII mode, this pin will be configured as TX_ER pin and will be sourced from MAC to PHY. Use of this pin is optional.
22 JTAG_TDO/GPIO_1 O JTAG TEST DATA OUTPUT: IEEE 1149.1 Test Data Output pin, the most recent test results are scanned out of the device via TDO.
General Purpose I/O: This signal provides a multi-function configurable I/O. Please refer to the GPIO_MUX_CTRL register for details.
23 JTAG_TMS I WPU JTAG TEST MODE SELECT: IEEE 1149.1 Test Mode Select pin, the TMS pin sequences the Tap Controller (16-state FSM) to select the desired test instruction. TI recommends that the user apply 3 clock cycles with JTAG_TMS high to reset the JTAG.
24 JTAG_TDI/SD I WPU JTAG TEST DATA INPUT: IEEE 1149.1 Test Data Input pin, test data is scanned into the device through the TDI.
SD: In 1000Base-X and 100Base-FX mode, this pin will act as Signal Detect. This should be connected to Signal Detect of optical transceiver.
25 TX_D3 I WPD TRANSMIT DATA: Signal TX_D[3:0] carries data from the MAC to the PHY in RGMII mode and MII mode. Data is synchronous to the transmit clock. In RGMII mode GTX_CLK is the transmit clock and in MII mode TX_CLK is the transmit clock.
26 TX_D2 I WPD
27 TX_D1 I WPD
28 TX_D0 I WPD
29 GTX_CLK/TX_CLK I/O WPD RGMII TRANSMIT CLOCK: This continuous clock signal is sourced from the MAC layer to the PHY. Nominal frequency is 125 MHz in 1000-Mbps mode. This pin will be Input in RGMII mode.
MII TRANSMIT CLOCK: In MII mode, this pin provides a 25-MHz reference clock for 100-Mbps speed and a 2.5-MHz reference clock for 10-Mbps speed. This pin will be output in MII mode. This pin will be GTX_CLK by default and can be changed to TX_CLK by register configurations.
30 VDDIO I Power I/O Power: 1.8 V (±5%), 2.5 V (±5%) or 3.3 V (±5%). Each pin requires a 1-µF and 0.1-µF capacitor to GND
31 VDD1P1 I Power 1.1-V Analog Supply (±10%). Each pin requires a 1-µF and 0.1-µF capacitor to GND.
32 RX_CLK O Strap, WPD RECEIVE CLOCK: Provides the recovered receive clocks for different modes of operation: 125 MHz in 1000-Mbps RGMII mode.
33 RX_D0 O Strap, WPD RECEIVE DATA: Signal RX_D[3:0] carries data from the PHY to the MAC in RGMII mode and in MII mode. Symbols received on the cable are decoded and presented on these pins synchronous to RX_CLK.
34 RX_D1 O Strap, WPD
35 RX_D2 O Strap, WPD
36 RX_D3 O Strap, WPD
37 TX_CTRL/TX_EN I WPD TRANSMIT CONTROL: In RGMII mode, TX_CTRL combines the transmit enable and the transmit error signal inputs from the MAC using both clock edges.
TX_EN: In MII mode, this pin will function as TX_EN.
38 RX_CTRL/RX_DV O WPD RECEIVE CONTROL: In RGMII mode, the receive data available and receive error are combined (RXDV_ER) using both rising and falling edges of the receive clock (RX_CLK).
RX_DV: In MII mode, this pin will function as RX_DV.
39 VDD1P1 I Power 1.1-V Analog Supply (±10%). Each pin requires a 1-µF and 0.1-µF capacitor to GND.
40 CLK_OUT O Clock CLOCK OUTPUT: Output clock
41 MDIO I/O MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the management station or the PHY. This open-drain pin requires a 1.5-kΩ pull-up resistor.
42 MDC I MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO serial management input/output data. This clock may be asynchronous to the MAC transmit and receive clocks. The maximum clock rate is 25-MHz. There is no minimum clock rate.
43 RESET_N I RESET_N: This pin is an active-low reset input that initializes or re-initializes all the internal registers of the DP83869. Asserting this pin low for at least 720 ns will force a reset process to occur. It is in IO voltage domain. Reset can be controlled by host controller. If that is not possible then a 100-Ω resistor and 47-uF capacitor are required to be connected in series between RESET_N pin and Ground. Refer to Reset Operation section of datasheet.
44 INT_N/PWDN_N I/O INTERRUPT / POWER DOWN: The default function of this pin is POWER DOWN.
POWER DOWN: This is an Active Low Input. Asserting this signal low enables the power-down mode of operation. In this mode, the device powers down and consumes minimum power. Register access is available through the Management Interface to configure and power up the device.
INTERRUPT: The interrupt pin is an open-drain, active low output signal indicating an interrupt condition has occurred. Register access is required to determine which event caused the interrupt. TI recommends using an external 2.2-kΩ resistor connected to the VDDIO supply. When register access is disabled through pin option, the interrupt will be asserted for 500 ms before self-clearing.
45 LED_2/GPIO_0 I/O Strap, WPD LED_2:This pin is part of the VDDIO voltage domain.
General Purpose I/O: This signal provides a multi-function configurable I/O. Please refer to the GPIO_MUX_CTRL register for details.
46 LED_1/RX_ER O Strap, WPD LED_1: This pin is part of the VDDIO voltage domain.
MII Mode: In MII mode this pin will be configured as RX_ER. This pin is asserted high synchronously to rising edge of RX_CLK. Use of this pin is optional.
47 LED_0 O Strap, WPD LED_0: This pin is part of the VDDIO voltage domain.
48 VDDA1P8_2 I Power No external supply is required for this pin in two-supply mode. When unused, no connections should be made to these pins. In three-supply mode, an external 1.8-V(±5%) supply can be connected to these pins. When using an external supply, each pin requires a 1-µF and 0.1-µF capacitor to GND.

    Pin Functionality definitions are given below

  • I: Input
  • O: Output
  • I/O: Input/Output
  • Strap: Multifunctional bootstrap pins
  • WPD: Weak Pull Down Resistor (internal)
  • WPU: Weak Pull Up Resistor (internal)
  • Power: Power Supply Pins
  • Analog: Analog pins

Table 1. Pin States-1

PIN NO PIN NAME RESET COPPER MODE
MII RGMII SGMII
PIN STATE PULL/HI-Z PIN STATE PULL/HI-Z PIN STATE PULL/HI-Z PIN STATE PULL/HI-Z
14 SON O Hi-Z O Hi-Z O Hi-Z O 50Ω
15 SOP O Hi-Z O Hi-Z O Hi-Z O 50Ω
16 SIP I Hi-Z I Hi-Z I Hi-Z I 50Ω
17 SIN I Hi-Z I Hi-Z I Hi-Z I 50Ω
21 JTAG_CLK/ TX_ER I PU I PU I PU I PU
22 JTAG_TDO / GPIO_1 I PD O Hi-Z O Hi-Z O Hi-Z
23 JTAG_TMS I PU I PU I PU I PU
24 JTAG_TDI / SD I PU I PU I PU I PU
25 TX_D3 I PD I PD I PD I PD
26 TX_D2 I PD I PD I PD I PD
27 TX_D1 I PD I PD I PD I PD
28 TX_D0 I PD I PD I PD I PD
29 GTX_CLK / TX_CLK I PD O PD I PD I PD
32 RX_CLK I PD O Hi-Z O (125MHz) Hi-Z I PD
33 RX_D0 I PD O Hi-Z O Hi-Z I PD
34 RX_D1 I PD O Hi-Z O Hi-Z I PD
35 RX_D2 I PD O Hi-Z O Hi-Z I PD
36 RX_D3 I PD O Hi-Z O Hi-Z I PD
37 TX_CTRL / TX_EN I PD I PD I PD I PD
38 RX_CTRL / RX_DV I PD O Hi-Z O Hi-Z I Hi-Z
40 CLK_OUT O (25MHz) Hi-Z O (25MHz) Hi-Z O (25MHz) Hi-Z O (25MHz) Hi-Z
41 MDIO I Hi-Z I/O Hi-Z I/O Hi-Z I/O Hi-Z
42 MDC I Hi-Z I Hi-Z I Hi-Z I Hi-Z
43 RESET_N I PU I PU I PU I PU
44 INT_N / PWDN_N I PU I/O PU/OD-PU I/O PU/OD-PU I/O PU/OD-PU
45 LED_2 / GPIO_0 I PD I/O Hi-Z I/O Hi-Z I/O Hi-Z
46 LED_1 / RX_ER I PD O Hi-Z O Hi-Z O Hi-Z
47 LED_0 I PD O Hi-Z O Hi-Z O Hi-Z

Table 2. Pin States-2

PIN NO PIN NAME MEDIA CONVERTOR BRIDGE MODE
RGMII TO SGMII SGMII TO RGMII
PIN STATE PULL/HI-Z PIN STATE PULL/HI-Z PIN STATE PULL/HI-Z
14 SON O 50Ω O 50Ω O 50Ω
15 SOP O 50Ω O 50Ω O 50Ω
16 SIP I 50Ω I 50Ω I 50Ω
17 SIN I 50Ω I 50Ω I 50Ω
21 JTAG_CLK/ TX_ER I PU I PU I PU
22 JTAG_TDO / GPIO_1 O Hi-Z O Hi-Z O Hi-Z
23 JTAG_TMS I PU I PU I PU
24 JTAG_TDI / SD I PU I PU I PU
25 TX_D3 I PD I PD I PD
26 TX_D2 I PD I PD I PD
27 TX_D1 I PD I PD I PD
28 TX_D0 I PD I PD I PD
29 GTX_CLK / TX_CLK I PD I PD I PD
32 RX_CLK I PD O Hi-Z O Hi-Z
33 RX_D0 I PD O Hi-Z O Hi-Z
34 RX_D1 I PD O Hi-Z O Hi-Z
36 RX_D2 I PD O Hi-Z O Hi-Z
36 RX_D3 I PD O Hi-Z O Hi-Z
37 TX_CTRL / TX_EN I PD I PD I PD
38 RX_CTRL / RX_DV I PD O Hi-Z O Hi-Z
40 CLK_OUT O (25MHz) Hi-Z O (25MHz) Hi-Z O (25MHz) Hi-Z
41 MDIO I/O Hi-Z I/O Hi-Z I/O Hi-Z
42 MDC I Hi-Z I Hi-Z I Hi-Z
43 RESET_N I PU I PU I PU
44 INT_N / PWDN_N I/O PU/OD-PU I/O PU/OD-PU I/O PU/OD-PU
45 LED_2 / GPIO_0 I/O Hi-Z I/O Hi-Z I/O Hi-Z
46 LED_1 / RX_ER O Hi-Z O Hi-Z O Hi-Z
47 LED_0 O Hi-Z O Hi-Z O Hi-Z

Table 3. Pin States-3

PIN NO PIN NAME IEEE PWDN MII ISOLATE
PIN STATE PULL/HI-Z PIN STATE PULL/HI-Z
14 SON O 50Ω O 50Ω
15 SOP O 50Ω O 50Ω
16 SIP I 50Ω I 50Ω
17 SIN I 50Ω I 50Ω
21 JTAG_CLK/ TX_ER I/O PU I PU
22 JTAG_TDO / GPIO_1 O Hi-Z O Hi-Z
23 JTAG_TMS I PU I PU
24 JTAG_TDI / SD I PU I PU
25 TX_D3 I PD I PD
26 TX_D2 I PD I PD
27 TX_D1 I PD I PD
28 TX_D0 I PD I PD
29 GTX_CLK / TX_CLK I PD I PD
32 RX_CLK O (2.5MHz) Hi-Z I PD
33 RX_D0 O Hi-Z I PD
34 RX_D1 O Hi-Z I PD
36 RX_D2 O Hi-Z I PD
36 RX_D3 O Hi-Z I PD
37 TX_CTRL / TX_EN I PD I PD
38 RX_CTRL / RX_DV O Hi-Z I PD
40 CLK_OUT O (25MHz) Hi-Z O (25MHz) Hi-Z
41 MDIO I Hi-Z I Hi-Z
42 MDC I Hi-Z I Hi-Z
43 RESET_N I PD I PU
44 INT_N / PWDN_N I/O PU/OD-PU I/O PU/OD-PU
45 LED_2 / GPIO_0 O Hi-Z O Hi-Z
46 LED_1 / RX_ER O Hi-Z O Hi-Z
47 LED_0 O Hi-Z O Hi-Z