9.6.1.34 RGMII_CTRL2 Register (Address = 0x33) [reset = 0x0]
RGMII_CTRL2 is shown in Figure 66 and described in Table 54.
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Figure 66. RGMII_CTRL2 Register
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
RESERVED |
R-0x0 |
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
RGMII_AF_BYPASS_EN |
RGMII_AF_BYPASS_DLY_EN |
LOW_LATENCY_10_100_EN |
RESERVED |
RESERVED |
R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 54. RGMII_CTRL2 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
15-5 |
RESERVED |
R |
0x0 |
Reserved
|
4 |
RGMII_AF_BYPASS_EN |
R/W |
0x0 |
RGMII Async FIFO Bypass Enable: 1 = Enable RGMII Async FIFO Bypass. 0 = Normal operation.
|
3 |
RGMII_AF_BYPASS_DLY_EN |
R/W |
0x0 |
RGMII Async FIFO Bypass Delay Enable: 1 = Delay RX_CLK when operating in 10/100 with RGMII. 0 = Normal operation
|
2 |
LOW_LATENCY_10_100_EN |
R/W |
0x0 |
Low Latency 10/100 Enable: 1 = Enable low latency in 10/100 operation. 0 = Normal operation.
|
1 |
RESERVED |
R/W |
0x0 |
Reserved
|
0 |
RESERVED |
R/W |
0x0 |
Reserved
|