9.6.1.47 TDR_SEG_DURATION1 Register (Address = 0x182) [reset = 0x5326]
TDR_SEG_DURATION1 is shown in Figure 79 and described in Table 67.
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Figure 79. TDR_SEG_DURATION1 Register
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
RESERVED |
TDR_SEG_DURATION_SEG3 |
TDR_SEG_DURATION_SEG2 |
R-0x0 |
R/W-0x14 |
R/W-0x19 |
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
TDR_SEG_DURATION_SEG2 |
TDR_SEG_DURATION_SEG1 |
R/W-0x19 |
R/W-0x6 |
|
Table 67. TDR_SEG_DURATION1 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
15 |
RESERVED |
R |
0x0 |
Reserved
|
14-10 |
TDR_SEG_DURATION_SEG3 |
R/W |
0x14 |
Number of 125MHz clock cycles to run for segment #3
|
9-5 |
TDR_SEG_DURATION_SEG2 |
R/W |
0x19 |
Number of 125MHz clock cycles to run for segment #2
|
4-0 |
TDR_SEG_DURATION_SEG1 |
R/W |
0x6 |
Number of 125MHz clock cycles to run for segment #1
|