9.6.1.48 TDR_SEG_DURATION2 Register (Address = 0x183) [reset = 0xA01E]
TDR_SEG_DURATION2 is shown in Figure 80 and described in Table 68.
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Figure 80. TDR_SEG_DURATION2 Register
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
TDR_SEG_DURATION_SEG5 |
R/W-0xA0 |
|
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
TDR_SEG_DURATION_SEG4 |
R-0x0 |
R/W-0x1E |
|
Table 68. TDR_SEG_DURATION2 Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
15-8 |
TDR_SEG_DURATION_SEG5 |
R/W |
0xA0 |
Number of 125MHz clock cycles to run for segment #5
|
7-6 |
RESERVED |
R |
0x0 |
Reserved
|
5-0 |
TDR_SEG_DURATION_SEG4 |
R/W |
0x1E |
Number of 125MHz clock cycles to run for segment #4
|