SNLS676A May   2022  – December 2025 DP83TC813R-Q1 , DP83TC813S-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Diagnostic Tool Kit
        1. 7.3.1.1 Signal Quality Indicator
        2. 7.3.1.2 Electrostatic Discharge Sensing
        3. 7.3.1.3 Time Domain Reflectometry
        4. 7.3.1.4 Voltage Sensing
        5. 7.3.1.5 BIST and Loopback Modes
          1. 7.3.1.5.1 Data Generator and Checker
          2. 7.3.1.5.2 xMII Loopback
          3. 7.3.1.5.3 PCS Loopback
          4. 7.3.1.5.4 Digital Loopback
          5. 7.3.1.5.5 Analog Loopback
          6. 7.3.1.5.6 Reverse Loopback
      2. 7.3.2 Compliance Test Modes
        1. 7.3.2.1 Test Mode 1
        2. 7.3.2.2 Test Mode 2
        3. 7.3.2.3 Test Mode 4
        4. 7.3.2.4 Test Mode 5
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power Down
      2. 7.4.2  Reset
      3. 7.4.3  Standby
      4. 7.4.4  Normal
      5. 7.4.5  Sleep Ack
      6. 7.4.6  Sleep Request
      7. 7.4.7  Sleep Fail
      8. 7.4.8  Sleep
      9. 7.4.9  Wake-Up
      10. 7.4.10 TC10 System Example
      11. 7.4.11 Media Dependent Interface
        1. 7.4.11.1 100BASE-T1 Leader and 100BASE-T1 Follower Configuration
        2. 7.4.11.2 Auto-Polarity Detection and Correction
        3. 7.4.11.3 Jabber Detection
        4. 7.4.11.4 Interleave Detection
      12. 7.4.12 MAC Interfaces
        1. 7.4.12.1 Media Independent Interface
        2. 7.4.12.2 Reduced Media Independent Interface
        3. 7.4.12.3 Reduced Gigabit Media Independent Interface
        4. 7.4.12.4 Serial Gigabit Media Independent Interface
      13. 7.4.13 Serial Management Interface
        1. 7.4.13.1 Direct Register Access
        2. 7.4.13.2 Extended Register Space Access
        3. 7.4.13.3 Write Operation (No Post Increment)
        4. 7.4.13.4 Read Operation (No Post Increment)
        5. 7.4.13.5 Write Operation (Post Increment)
        6. 7.4.13.6 Read Operation (Post Increment)
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 PHY Address Configuration
  9. 8 Register Maps
    1. 8.1 Register Access Summary
    2. 8.2 DP83TC813 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Physical Medium Attachment
          1. 9.2.1.1.1 Common-Mode Choke Recommendations
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Signal Traces
        2. 9.4.1.2 Return Path
        3. 9.4.1.3 Metal Pour
        4. 9.4.1.4 PCB Layer Stacking
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Community Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.1 Strap Configuration

The DP83TC813S-Q1 uses functional pins as strap options to place the device into specific modes of operation. The values of these pins are sampled at power up and hardware reset (through either the RESET pin or register access). Some strap pins support 3 levels and some strap pins support 2 levels, which are described in greater detail below. PHY address straps, RX_DV/RX_CTRL and RX_ER, are 3-level straps while all other straps are two levels. Configuration of the device can be done through strapping or through serial management interface.

Note:

Because strap pins are functional pins after reset is deasserted, strap pins must not be connected directly to VDDIO or VDDMAC or GND. Either pullup resistors, pulldown resistors, or both are required for proper operation.

Note:

When using VDDMAC and VDDIO separately, connect strap resistors to the correct voltage rail. The voltage domain of each pin is listed in the table below.

DP83TC813S-Q1 DP83TC813R-Q1 Strap CircuitFigure 7-18 Strap Circuit

Rpulldn value is included in the Electrical Characteristics table of the data sheet.

Table 7-18 Recommended 3-Level Strap Resistor Ratios for PHY Address
MODE3IDEAL RH (kΩ) (VDDIO = 3.3V)1IDEAL RH (kΩ) (VDDIO = 2.5V)2IDEAL RH (kΩ) (VDDIO = 1.8V)1
1OPENOPENOPEN
213124
34.520.8
  1. Strap resistors with 10% tolerance.
  2. Strap resistors with 1% tolerance.
  3. RL is optional and can be added if voltage on bootstrap pins needs to be adjusted.
Table 7-19 Recommended 2-Level Strap Resistors
MODEIDEAL RH (kΩ)(1), (2)
1OPEN
22.49
(1) Strap resistors with up to 10% tolerance can be used.
(2) To gain more margin in customer application for 1.8V VDDIO, either 2.1kΩ +/-10% pull-up can be used or resistor accuracy of 2.49kΩ resistor can be limited to 1%.

The following table describes the PHY configuration bootstraps:

Table 7-20 Bootstraps
PIN
NAME		PIN NO.DOMAINDEFAULT
MODE		STRAP FUNCTIONDESCRIPTION
RX_DV/RX_CTRL

22

VDDMAC1MODEPHY_AD[0]PHY_AD[2]PHY_AD: PHY Address ID
100
201
311
RX_ER21VDDMAC1MODEPHY_AD[1]PHY_AD[3]PHY_AD: PHY Address ID
100
201
311
RX_CLK28VDDMAC1MODEAUTOAUTO: Autonomous Disable.
10
21
RX_D027VDDMAC1MODEMAC[0]MAC: MAC Interface Selection
10
21
RX_D126VDDMAC1MODEMAC[1]MAC: MAC Interface Selection
10
21
RX_D225VDDMAC1MODEMAC[2]MAC: MAC Interface Selection
10
21
RX_D324VDDMAC1MODEMSMS: 100BASE-T1 Leader and 100BASE-T1 Follower Selection
10
2 1
Note: Refer to SNLA389 Application Note for more information about the register settings used for compliance testing. Use these register settings to achieve the same performance as observed during compliance testing. Managed mode strap option is recommended to prevent the link up process from initiating while the software configuration from SNLA389 is being executed. Once the software configuration is completed, the PHY can be removed from Managed mode by setting bit 0x018B[6] to ‘1’. This bit is auto-cleared after link up
Table 7-21 100BASE-T1 Leader and 100BASE-T1 Follower Selection Bootstrap
MSDESCRIPTION
0100BASE-T1 Follower Configuration
1100BASE-T1 Leader Configuration
Table 7-22 Autonomous Mode Bootstrap
AUTODESCRIPTION
0Autonomous Mode, PHY able to establish link after power-up
1Managed Mode, PHY must be allowed to establish link after power-up based on register write
Table 7-23 MAC Interface Selection Bootstraps
MAC[2]MAC[1]MAC[0]DESCRIPTION
000SGMII (4-wire)(1)
001MII
010RMII

Follower

011RMII

Leader

100RGMII (Align Mode)
101RGMII (TX Internal Delay Mode)
110RGMII (TX and RX Internal Delay Mode)
111RGMII (RX Internal Delay Mode)
(1) SGMII strap mode is only available on 'S' type device variant. For 'R' type device variant, this strap mode is RESERVED
Table 7-24 PHY Address Bootstraps
PHY_AD[3:0]RX_CTRL STRAP MODERX_ER STRAP MODEDESCRIPTION Section 7.5.1
000011PHY Address: 0b00000 (0x0)
0001--NA
0010--NA
0011--NA
010021PHY Address: 0b00100 (0x4)
010131PHY Address: 0b00101 (0x5)
0110--NA
0111--NA
100012PHY Address: 0b01000 (0x8)
1001--NA
101013PHY Address: 0b01010 (0xA)
1011--NA
110022PHY Address: 0b01100 (0xC)
110132PHY Address: 0b01101 (0xD)
111023PHY Address: 0b01110 (0xE)
111133PHY Address: 0b01111 (0xF)