RX_D3

Receive Data: Symbols received on the cable are decoded and transmitted out of these pins synchronous to the rising edge of RX_CLK. They contain valid data when RX_DV(decoded from RX_CTL) is asserted. A nibble, RX_D[3:0], is transmitted in RGMII mode.

RX_D2

RX_D1

RX_D0

Receive Clock: In RGMII mode, PHY provides this 125-MHz clock to MAC.

RGMII Receive Control: Receive control combines receive data valid indication and receive error indication into a single signal. RX_DV is presented on the rising edge of RX_CLK and RX_ER is presented on the falling edge of RX_CLK.

Transmit Clock: In RGMII mode, MAC provides this 125-MHz clock to PHY.

RGMII Transmit Control: Transmit control combines transmit enable and transmit error indication into a single signal. TX_EN is presented prior to the rising edge of TX_CLK; TX_ER is presented on the falling edge of TX_CLK.

Transmit Data: In RGMII mode, the transmit data nibble, TX_D[3:0], is received from the MAC .

TX_D1

TX_D0

Management Data Clock: Synchronous clock to the MDIO serial management input and output data.

Management Data Input/Output: Bidirectional management data signal that may be sourced by the management station or the PHY. This pin requires an external pull-up resistor (recommended value = 2.2-kΩ) .

Interrupt: Active-LOW output, which will be asserted LOW when an interrupt condition occurs. This pin has a weak internal pullup. Register access is necessary to enable various interrupt triggers. Once an interrupt event flag is set, register access is required to clear the interrupt event on this pin.

This pin can be configured as an Active-HIGH output using register[0x0011].

To capture the interrupt source reliably, status from interrupt registers x12, x13, x18 is recommended to be read after interrupt is asserted on int_n pin.

RESET: Active-LOW input, which initializes or reinitializes the DP83TG720R-Q1. Asserting this pin LOW for at least 10 μs will force a reset process to occur. All internal registers will reinitialize to their default states as specified for each bit in the Register Map section. All bootstrap pins are resampled upon deassertion of reset.

INH: Active-HIGH PMOS open-drain output. When the PHY enters the sleep state, PHY will release the INH pin to allow an external pull-down resistor (recommended value = 10 kΩ) to pull the line to ground. When in any other state, the INH pin will drive a HIGH state to the VSLEEP rail.

WAKE: Active-HIGH (this pin works on VSLEEP domain) pulse on wake-up pin wakes up the PHY from the sleep state. For pulse width, refer to timing section. This pin can be directly tied to the VSLEEP rail when the sleep state is not used or left float.

Strap 1: This pin is for strapping PHY_AD bits.

Reference Clock Input: Reference clock 25-MHz ±100 ppm-tolerance crystal or oscillator input. The device supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator connected to pin XI only and XO left floating.

Reference Clock Output: XO pin is used for crystal only. This pin should be left floating when a CMOS-level oscillator is connected to XI.

LED_0: Link Status

LED_1: Link Status and BLINK for TX/RX Activity

Clock Output: 25-MHz reference clock(buffered replication of XI) by default. If not used, clock output can be disabled by writing register 0x0453 = 0x0006.

Differential Transmit and Receive: Bidirectional differential signaling configured for 1000BASE-T1 operation, IEEE 802.3bp compliant.