SPRS956H March 2016 – November 2019 DRA722 , DRA724 , DRA725 , DRA726
Refer to the PDF data sheet for device specific package drawings
No matter the number of DDR3 devices used, the data line topology is always point to point, so its definition is simple.
Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure there are nearby ground vias to allow the return currents to transition between reference planes if both reference planes are ground or vdds_ddr. Ensure there are nearby bypass capacitors to allow the return currents to transition between reference planes if one of the reference planes is ground. The goal is to minimize the size of the return current loops.